According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barrier...According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas：extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k （MHK） gate stack, ultra-shallow junction （USJ） and other strain enhancement engineering methods, including stress proximity effect （SPT）, dual stress liner （DSL）, stress memorization technique （SMT）, high aspect ratio process （HARP） for STI and PMD,embedded SiGe （for pFET） and SiC （for nFET） source/drain （S/D） using selective epitaxial growth （SEG） method,metallization for middle of line （MOL） and back-end of line （BEOL） ,and ultra low-k （ULK） integration.展开更多
In this paper, we consider a network communication delay improvement problem,which is to upgrade nodes in a network with minimum cost such that the communication delay betweenany two nodes of the network is below a pr...In this paper, we consider a network communication delay improvement problem,which is to upgrade nodes in a network with minimum cost such that the communication delay betweenany two nodes of the network is below a pre-specific level. In the upgrading model, the improvementby upgrading one node is a continuous variable, and the cost incurred by such an upgrading is alinear function of the improvement. We show that achieving an approximation ratio βln(|V|) for theproblem is NP-hard for some constant β > 0 even if the underlying network is a bipartite graph. Butif the underlying network is restricted as a tree, we show that it can be solved in a stronglypolynomial time.展开更多
文摘According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas：extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k （MHK） gate stack, ultra-shallow junction （USJ） and other strain enhancement engineering methods, including stress proximity effect （SPT）, dual stress liner （DSL）, stress memorization technique （SMT）, high aspect ratio process （HARP） for STI and PMD,embedded SiGe （for pFET） and SiC （for nFET） source/drain （S/D） using selective epitaxial growth （SEG） method,metallization for middle of line （MOL） and back-end of line （BEOL） ,and ultra low-k （ULK） integration.
基金This research is supported by National Key Researchand Development Programof China(No.2002CB312004)and the National Outstanding Youth Fund.
文摘In this paper, we consider a network communication delay improvement problem,which is to upgrade nodes in a network with minimum cost such that the communication delay betweenany two nodes of the network is below a pre-specific level. In the upgrading model, the improvementby upgrading one node is a continuous variable, and the cost incurred by such an upgrading is alinear function of the improvement. We show that achieving an approximation ratio βln(|V|) for theproblem is NP-hard for some constant β > 0 even if the underlying network is a bipartite graph. Butif the underlying network is restricted as a tree, we show that it can be solved in a stronglypolynomial time.
