According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barrier...According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas：extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k （MHK） gate stack, ultra-shallow junction （USJ） and other strain enhancement engineering methods, including stress proximity effect （SPT）, dual stress liner （DSL）, stress memorization technique （SMT）, high aspect ratio process （HARP） for STI and PMD,embedded SiGe （for pFET） and SiC （for nFET） source/drain （S/D） using selective epitaxial growth （SEG） method,metallization for middle of line （MOL） and back-end of line （BEOL） ,and ultra low-k （ULK） integration.展开更多
The paper studies the metallurgical energy saving standards system, indicates the current siltutinon of standards and proposes a plan for the further standardizalion work. so as to promote new energy saving technologi...The paper studies the metallurgical energy saving standards system, indicates the current siltutinon of standards and proposes a plan for the further standardizalion work. so as to promote new energy saving technologies and application of new process to boost energy eonservation and emission reduction.展开更多
Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field ...Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4(BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced,which only needs a few technology parameters.With this transistor intrinsic gain model,complementary metal-oxide-semiconductor(CMOS) operational amplifier(op amp) DC gain could be predicted.A two-stage folded cascode op amp is used as an example in this work.Non-minimum length device is used to improve the op amp DC gain.An improvement of 20 dB is proved when using doubled channel length design.Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain.After these,a full op amp DC gain scaling roadmap is proposed,from 130 nm technology node to 32 nm technology node.Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB.Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology.The prediction based on our simplified gain model agrees with SPICE simulation results.展开更多
文摘According to the international technology roadmap for semiconductors （ITRS）,32nm technology node will be introduced around 2009. Scaling of CMOS logic devices from 45 to 32nm node has come across significant barriers. Overcoming these pitch-scaling induced barriers requires integrating the most advanced process technologies into product manufacturing. This paper reviews and discusses new technology applications that could be potentially integrated into 32nm node in the following areas：extension of immersion lithography,mobility enhancement substrate technology,metal/ high-k （MHK） gate stack, ultra-shallow junction （USJ） and other strain enhancement engineering methods, including stress proximity effect （SPT）, dual stress liner （DSL）, stress memorization technique （SMT）, high aspect ratio process （HARP） for STI and PMD,embedded SiGe （for pFET） and SiC （for nFET） source/drain （S/D） using selective epitaxial growth （SEG） method,metallization for middle of line （MOL） and back-end of line （BEOL） ,and ultra low-k （ULK） integration.
文摘The paper studies the metallurgical energy saving standards system, indicates the current siltutinon of standards and proposes a plan for the further standardizalion work. so as to promote new energy saving technologies and application of new process to boost energy eonservation and emission reduction.
文摘Metal-oxide-semiconductor field effect transistor(MOSFET) intrinsic gain degradation caused by channel length modulation(CLM) effect is examined.A simplified model based on Berkeley short-channel insulator-gate field effect transistor model version 4(BSIM4) current expression for sub-100 nm MOSFET intrinsic gain is deduced,which only needs a few technology parameters.With this transistor intrinsic gain model,complementary metal-oxide-semiconductor(CMOS) operational amplifier(op amp) DC gain could be predicted.A two-stage folded cascode op amp is used as an example in this work.Non-minimum length device is used to improve the op amp DC gain.An improvement of 20 dB is proved when using doubled channel length design.Optimizing transistor bias condition and using advanced technology with thinner gate dielectric thickness and shallower source/drain junction depth can also increase the op amp DC gain.After these,a full op amp DC gain scaling roadmap is proposed,from 130 nm technology node to 32 nm technology node.Five scaled op amps are built and their DC gains in simulation roll down from 69.6 to 41.1 dB.Simulation shows transistors biased at higher source-drain voltage will have more impact on the op amp DC gain scaling over technology.The prediction based on our simplified gain model agrees with SPICE simulation results.
