The Image sensor needs various image processing by Image Signal Processor （ISP） to improve image quality. Conventional cameras have their own software ISP functions to perform in PC instead of using commercial ISP c...The Image sensor needs various image processing by Image Signal Processor （ISP） to improve image quality. Conventional cameras have their own software ISP functions to perform in PC instead of using commercial ISP chips. However these methods have problems such as large computation for image processing. In this paper, th authors proposed ISP that significantly reduced chip area by efficiently sharing of hardware and software. Large operation blocks are designed to hardware for high performances, and hardware is imployed simultaneously with software considering the size of the hardware. The implemented ISP can process Video Graphics Array （VGA） （640 ＊ 480） images and has 91 450 gates size in 0. 35 μm process.展开更多
The function-layer model and working model of collaborative remote fault diagnosis system （FDS）, which includes three layers： task layer, collaboration layer and diagnosing layer, are proposed. The running mechanis...The function-layer model and working model of collaborative remote fault diagnosis system （FDS）, which includes three layers： task layer, collaboration layer and diagnosing layer, are proposed. The running mechanism of the system is discussed. A collaborative FDS may consist of several subsystems running at different places and the subsystem consists of several fimction modules. A structure centered on data-bus is adopted in subsystem. All the function modules in subsystem are encapsulated into software intelligent chips （SICs） and SIC can but connect with data-bus. So, it is feasible to reuse these diagnosis fimction modules and the structure of subsystem in different diagnosis applications. With the reconfigurable SICs, several different function modules can reconstruct quickly some different diagnosis subsystems in different combinations, and some subsystems can also reconfigure a specified collaborative FDS.展开更多
Design optimization of a novel integrated triplexer based on planar lightwave circuit (PLC) for fiber-to-the-home applica- tions is described. The two-mode interference coupler and Mach-Zehnder interference are used t...Design optimization of a novel integrated triplexer based on planar lightwave circuit (PLC) for fiber-to-the-home applica- tions is described. The two-mode interference coupler and Mach-Zehnder interference are used to construct the filter chip. Simulation results of high isolation and low insertion loss are gotten for proposed design. Technique tolerance is improved for fabricating device.展开更多
This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog...This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.展开更多
Corn cobs are a promising lignocellulosic substrate for the production of biofuels like bioethanol via conventional yeast or biodiesel via oleaginous yeast. Pretreatment of the substrate is essential for further hydro...Corn cobs are a promising lignocellulosic substrate for the production of biofuels like bioethanol via conventional yeast or biodiesel via oleaginous yeast. Pretreatment of the substrate is essential for further hydrolysis and fermentation steps. This study focused on the steam explosion method as pretreatment. Therefore, different steam explosion severities were evaluated. The content of glucan, xylan and Klason lignin was examined. Xylan degraded with increasing severity from 412.7 g·kg-1 （untreated） to a minimum of 127.3 g-kg1 dry matter （190 ℃/30 min）. Glucan concentrations increased from 315.1 g·kg1 （untreated） to a maximum of 371.6 g·kg-1 dry matter （200 ℃/20 min）. For soluble lignin, an increase could be observed at rising severity, from 145.3 g·kg-l （untreated） to a maximum of 214.9 g·kg-1 dry matter （190 ℃/30 min）. Furthermore, the mass recovery was calculated. At harsher pretreatment conditions, a significant mass loss was observed, estimated by the ash content in the recovered dry matter. The lowest recovery rate was observed for SF = 4.13 （190 ℃/30 min） with 68.39%. The produced inhibitors were evaluated.展开更多
Helper-thread of a task can hide the memory access time of irregular data on the chip muhi-core processor （CMP）. For constructing a compiler that effectively supports the helper-thread of a task in the multi-core sc...Helper-thread of a task can hide the memory access time of irregular data on the chip muhi-core processor （CMP）. For constructing a compiler that effectively supports the helper-thread of a task in the multi-core scenario based on the last level shared cache, this paper studies its performance stable condi- tions. Unfortunately, there is no existing model that allows extensive investigation of the impact of stable conditions, we present the base of pre-computation that is formalized by our degraded task-pair 〈 T, T＇ 〉 with the helper-thread, and its stable conditions are analyzed. Finally, a novel performance model and a constructing method of pre-computation based on our positive degraded task-pair are proposed. The efficient results are shown by our experiments. If we further exploit memory level parallelism （MLP） for our task-pair, the task-pair 〈 T, T＇ 〉 can reach better performance.展开更多
Although plating is a necessary process for SMT components, it alters the magnetic characteristics and inductance level of Ni-Cu-Zn ferrite components. The results of this work show that the following three factors in...Although plating is a necessary process for SMT components, it alters the magnetic characteristics and inductance level of Ni-Cu-Zn ferrite components. The results of this work show that the following three factors in plating affect these components, and the effects are different for Ni- and Sn-plating： （1） Plating layers exert stresses and react with the residual stress of components to change the inductance level, and the effect of the tin layer is greater than that of the nickel one; （2） The plating current induces a magnetic field inside the components directly and indirectly, and this remains as remanence inside the components and reduces the inductance level, and the effect level of Ni-plating is greater than that of Sn-plating; （3） The plating solution corrodes the interface of the termination and ferrite core of the components to release the residual stress, and causes an increase in inductance, and the effect of Sn-plating is greater than that of Ni-plating. In addition, the inductance level is the result of the net effect of these three factors, and if the sintering temperature is increased to change in the type of residual stress, the net effect will be changed.展开更多
To improve the efficiency of nano-electronic device fabrication, a new method named floating electrical potential assembly is proposed to realize large-scale assembly of Cu/CuO nanowires, The simulation of floating el...To improve the efficiency of nano-electronic device fabrication, a new method named floating electrical potential assembly is proposed to realize large-scale assembly of Cu/CuO nanowires, The simulation of floating electrical potential distribution on the micro-electrode chip is performed by COMSOL software, and the simulation result shows that the coupled electrical poten- tial on the floating drain electrodes is very close to the original electrical potential applied on the gate electrode, whicb means that the method can provide di-electrophoresis （DEP） force for all the electrode pairs at one time, thus realizing large-scale as- sembly at one time. With Cu/CuO nanowires well dispersed and micro-electrode chip fabrication, nanowires assembly experiments are performed and the experimental results show that Cu/CuO nanowires are assembled at hundreds of micro-electrodes pairs at one time, and the success rate of nanowires assembly also reaches 90%.展开更多
基金sponsored by ETRI System Semiconductor Industry Promotion Center,Human Resource Development Project for SoC Convergence and“System IC2010”project of Korea Ministry of Knowledge Economy
文摘The Image sensor needs various image processing by Image Signal Processor （ISP） to improve image quality. Conventional cameras have their own software ISP functions to perform in PC instead of using commercial ISP chips. However these methods have problems such as large computation for image processing. In this paper, th authors proposed ISP that significantly reduced chip area by efficiently sharing of hardware and software. Large operation blocks are designed to hardware for high performances, and hardware is imployed simultaneously with software considering the size of the hardware. The implemented ISP can process Video Graphics Array （VGA） （640 ＊ 480） images and has 91 450 gates size in 0. 35 μm process.
文摘The function-layer model and working model of collaborative remote fault diagnosis system （FDS）, which includes three layers： task layer, collaboration layer and diagnosing layer, are proposed. The running mechanism of the system is discussed. A collaborative FDS may consist of several subsystems running at different places and the subsystem consists of several fimction modules. A structure centered on data-bus is adopted in subsystem. All the function modules in subsystem are encapsulated into software intelligent chips （SICs） and SIC can but connect with data-bus. So, it is feasible to reuse these diagnosis fimction modules and the structure of subsystem in different diagnosis applications. With the reconfigurable SICs, several different function modules can reconstruct quickly some different diagnosis subsystems in different combinations, and some subsystems can also reconfigure a specified collaborative FDS.
文摘Design optimization of a novel integrated triplexer based on planar lightwave circuit (PLC) for fiber-to-the-home applica- tions is described. The two-mode interference coupler and Mach-Zehnder interference are used to construct the filter chip. Simulation results of high isolation and low insertion loss are gotten for proposed design. Technique tolerance is improved for fabricating device.
文摘This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.
文摘Corn cobs are a promising lignocellulosic substrate for the production of biofuels like bioethanol via conventional yeast or biodiesel via oleaginous yeast. Pretreatment of the substrate is essential for further hydrolysis and fermentation steps. This study focused on the steam explosion method as pretreatment. Therefore, different steam explosion severities were evaluated. The content of glucan, xylan and Klason lignin was examined. Xylan degraded with increasing severity from 412.7 g·kg-1 （untreated） to a minimum of 127.3 g-kg1 dry matter （190 ℃/30 min）. Glucan concentrations increased from 315.1 g·kg1 （untreated） to a maximum of 371.6 g·kg-1 dry matter （200 ℃/20 min）. For soluble lignin, an increase could be observed at rising severity, from 145.3 g·kg-l （untreated） to a maximum of 214.9 g·kg-1 dry matter （190 ℃/30 min）. Furthermore, the mass recovery was calculated. At harsher pretreatment conditions, a significant mass loss was observed, estimated by the ash content in the recovered dry matter. The lowest recovery rate was observed for SF = 4.13 （190 ℃/30 min） with 68.39%. The produced inhibitors were evaluated.
文摘Helper-thread of a task can hide the memory access time of irregular data on the chip muhi-core processor （CMP）. For constructing a compiler that effectively supports the helper-thread of a task in the multi-core scenario based on the last level shared cache, this paper studies its performance stable condi- tions. Unfortunately, there is no existing model that allows extensive investigation of the impact of stable conditions, we present the base of pre-computation that is formalized by our degraded task-pair 〈 T, T＇ 〉 with the helper-thread, and its stable conditions are analyzed. Finally, a novel performance model and a constructing method of pre-computation based on our positive degraded task-pair are proposed. The efficient results are shown by our experiments. If we further exploit memory level parallelism （MLP） for our task-pair, the task-pair 〈 T, T＇ 〉 can reach better performance.
文摘Although plating is a necessary process for SMT components, it alters the magnetic characteristics and inductance level of Ni-Cu-Zn ferrite components. The results of this work show that the following three factors in plating affect these components, and the effects are different for Ni- and Sn-plating： （1） Plating layers exert stresses and react with the residual stress of components to change the inductance level, and the effect of the tin layer is greater than that of the nickel one; （2） The plating current induces a magnetic field inside the components directly and indirectly, and this remains as remanence inside the components and reduces the inductance level, and the effect level of Ni-plating is greater than that of Sn-plating; （3） The plating solution corrodes the interface of the termination and ferrite core of the components to release the residual stress, and causes an increase in inductance, and the effect of Sn-plating is greater than that of Ni-plating. In addition, the inductance level is the result of the net effect of these three factors, and if the sintering temperature is increased to change in the type of residual stress, the net effect will be changed.
基金supported by the National Natural Science Foundation of China(Grant No.51005230)China Postdoctoral Science Foundation(Grant No.2012M520654)the Education Department of Liaoning Province Science and Ttechnology Research Projects(Grant No.L2012213)
文摘To improve the efficiency of nano-electronic device fabrication, a new method named floating electrical potential assembly is proposed to realize large-scale assembly of Cu/CuO nanowires, The simulation of floating electrical potential distribution on the micro-electrode chip is performed by COMSOL software, and the simulation result shows that the coupled electrical poten- tial on the floating drain electrodes is very close to the original electrical potential applied on the gate electrode, whicb means that the method can provide di-electrophoresis （DEP） force for all the electrode pairs at one time, thus realizing large-scale as- sembly at one time. With Cu/CuO nanowires well dispersed and micro-electrode chip fabrication, nanowires assembly experiments are performed and the experimental results show that Cu/CuO nanowires are assembled at hundreds of micro-electrodes pairs at one time, and the success rate of nanowires assembly also reaches 90%.
