服务元是近期开始研究的一种非层次网络体系结构,采用虚电路VC(V irtual C ircu it)结构。如用于专用的测控网络系统,能提高其实时性能。针对测控网络的服务元体系结构用着色Petri网CPN(Colored PetriNet)建模,采用的不是通常自顶而下...服务元是近期开始研究的一种非层次网络体系结构,采用虚电路VC(V irtual C ircu it)结构。如用于专用的测控网络系统,能提高其实时性能。针对测控网络的服务元体系结构用着色Petri网CPN(Colored PetriNet)建模,采用的不是通常自顶而下分级的方法,而是提出了统一建模的思想,用少量复杂的库所、变迁表示模型,给出了网络界熟悉的收发操作算法,提出了两次握手协议和六次握手协议。测控网络采用VC结构,能提高测控网络的实时服务质量QoS(Quality of Server),用CPN工具建模仿真可分析测控网络的性能。展开更多
A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral com...A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.展开更多
文摘服务元是近期开始研究的一种非层次网络体系结构,采用虚电路VC(V irtual C ircu it)结构。如用于专用的测控网络系统,能提高其实时性能。针对测控网络的服务元体系结构用着色Petri网CPN(Colored PetriNet)建模,采用的不是通常自顶而下分级的方法,而是提出了统一建模的思想,用少量复杂的库所、变迁表示模型,给出了网络界熟悉的收发操作算法,提出了两次握手协议和六次握手协议。测控网络采用VC结构,能提高测控网络的实时服务质量QoS(Quality of Server),用CPN工具建模仿真可分析测控网络的性能。
基金Projects(61203308,61309014)supported by the National Natural Science Foundation of China
文摘A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches.
