A 30Gbit/s receptor module is developed with a CMOS integrated receiver chip（IC） and a GaAs-based 1 × 12 photo detector array of PIN-type. Parallel technology is adopted in this module to realize a high-speed r...A 30Gbit/s receptor module is developed with a CMOS integrated receiver chip（IC） and a GaAs-based 1 × 12 photo detector array of PIN-type. Parallel technology is adopted in this module to realize a high-speed receiver module with medium speed devices. A high-speed printed circuit board（PCB） is designed and produced. The IC chip and the PD array are packaged on the PCB by chip-on-board technology. Flip chip alignment is used for the PD array accurately assembled on the module so that a plug-type optical port is built. Test results show that the module can receive parallel signals at 30Gbit/s. The sensitivity of the module is - 13.6dBm for 10^-13 BER.展开更多
Properties of the active power/angle sub-matrix in the power flow Jacobian for power system analysis are studied. The sub-matrix is a dominant and irreducible matrix under very general conditions of power systems, so ...Properties of the active power/angle sub-matrix in the power flow Jacobian for power system analysis are studied. The sub-matrix is a dominant and irreducible matrix under very general conditions of power systems, so that it is invertible. Also the necessary conditions for its singularity are given. These theoretical results can be used to clarify the ambiguous understanding of the sub-matrix in current literature, and also provide the theoretical foundations for the applications based on reduced power flow Jaeobian. Numerical simulation on the IEEE 118-bus power system is used to illustrate our results.展开更多
文摘A 30Gbit/s receptor module is developed with a CMOS integrated receiver chip（IC） and a GaAs-based 1 × 12 photo detector array of PIN-type. Parallel technology is adopted in this module to realize a high-speed receiver module with medium speed devices. A high-speed printed circuit board（PCB） is designed and produced. The IC chip and the PD array are packaged on the PCB by chip-on-board technology. Flip chip alignment is used for the PD array accurately assembled on the module so that a plug-type optical port is built. Test results show that the module can receive parallel signals at 30Gbit/s. The sensitivity of the module is - 13.6dBm for 10^-13 BER.
基金the National Natural Science Foundation of China (No. 50307007)
文摘Properties of the active power/angle sub-matrix in the power flow Jacobian for power system analysis are studied. The sub-matrix is a dominant and irreducible matrix under very general conditions of power systems, so that it is invertible. Also the necessary conditions for its singularity are given. These theoretical results can be used to clarify the ambiguous understanding of the sub-matrix in current literature, and also provide the theoretical foundations for the applications based on reduced power flow Jaeobian. Numerical simulation on the IEEE 118-bus power system is used to illustrate our results.
