A Single-Buffered （SB） router is a router where only one stage of shared buffering is sandwiched between two interconnects in comparison of a Combined Input and Output Queued （CIOQ） router where a central switch f...A Single-Buffered （SB） router is a router where only one stage of shared buffering is sandwiched between two interconnects in comparison of a Combined Input and Output Queued （CIOQ） router where a central switch fabric is sandwiched between two stages of buffering. The notion of SB routers was firstly proposed by the High-Performance Networking Group （HPNG） of Stanford University, along with two promising designs of SB routers： one of which was Parallel Shared Memory （PSM） router and the other was Distributed Shared Memory （DSM） router. Admittedly, the work of HPNG deserved full credit, but all results presented by them appeared to relay on a Centralized Memory Management Algorithm （CMMA） which was essentially impractical because of the high processing and communication complexity. This paper attempts to make a scalable high-speed SB router completely practical by introducing a fully distributed architecture for managing the shared memory of SB routers. The resulting SB router is called as a Virtual Output and Input Queued （VOIQ） router. Furthermore, the scheme of VOIQ routers can not only eliminate the need for the CMMA scheduler, thus allowing a fully distributed implementation with low processing and commu- nication complexity, but also provide QoS guarantees and efficiently support variable-length packets in this paper. In particular, the results of performance testing and the hardware implementation of our VOIQ-based router （NDSC~ SR1880-TTM series） are illustrated at the end of this paper. The proposal of this paper is the first distributed scheme of how to design and implement SB routers publicized till now.展开更多
In order to optimize the electricity yield of CSP （concentrated solar power） plants, TES （thermal energy storage） systems are regarded as an essential component. Furthermore, for many electricity grid operators, i...In order to optimize the electricity yield of CSP （concentrated solar power） plants, TES （thermal energy storage） systems are regarded as an essential component. Furthermore, for many electricity grid operators, it is important to have spinning reserves in the grid and dispatchable power available, both offered by CSP-plants with integrated thermal energy storage. Enolcon is developing a new TES-system since several years. The system itself was designed to offer a principle simple and robust setup （with regard to execution and operation） and which is reducing the electricity costs of CSP-power plants by the consequent use of state of the art technology. Furthermore, such system shall be open to future developments of CSP-systems with regard to increasing steam temperatures and steam pressure. Such TES-system shall be commercially available for large scale application already in year 2014/2015. The key elements of the enolcon-TES are the open cycle using always ambient air with an air-air-heat exchanger and the arrangement of the storage material in such way to minimize the pressure losses and the own electricity consumption. The development is progressing in a structured way by studies, engineering works, TES-pilot plants, isothermal air flow test plant for the verification of the CFD-calculations, and since end of 2012 by the operation of a high temperature TES-module with all features of the large scale modules.展开更多
This work presents a self-consistent two-dimensional(2-D) simulation method with unified physical models for different operation regimes of charge trapping memory. The simulation carefully takes into consideration the...This work presents a self-consistent two-dimensional(2-D) simulation method with unified physical models for different operation regimes of charge trapping memory. The simulation carefully takes into consideration the tunneling process, charge trapping/de-trapping mechanisms, and 2-D drift-diffusion transport within the storage layer. A string of three memory cells has been simulated and evaluated for different gate stack compositions and temperatures. The simulator is able to describe the charge transport behavior along bitline and tunneling directions under different operations. Good agreement has been made with experimental data,which hence validates the implemented physical models and altogether confirms the simulation as a valuable tool for evaluating the characteristics of three-dimensional NAND flash memory.展开更多
Consistent high-quality and defect-free production is the demand of the day. The product recall not only increases engineering and manufacturing cost but also affects the quality and the reliability of the product in ...Consistent high-quality and defect-free production is the demand of the day. The product recall not only increases engineering and manufacturing cost but also affects the quality and the reliability of the product in the eye of users. The monitoring and improvement of a manufacturing process are the strength of statistical process control. In this article we propose a process monitoring memory-based scheme for continuous data under the assumption of normality to detect small non-random shift patterns in any manufacturing or service process.The control limits for the proposed scheme are constructed. The in-control and out-of-control average run length(AVL) expressions have been derived for the performance evaluation of the proposed scheme. Robustness to non-normality has been tested after simulation study of the run length distribution of the proposed scheme, and the comparisons with Shewhart and exponentially weighted moving average(EWMA) schemes are presented for various gamma and t-distributions. The proposed scheme is effective and attractive as it has one design parameter which differentiates it from the traditional schemes. Finally, some suggestions and recommendations are made for the future work.展开更多
基金the National High-Tech Research and De-velopment Program of China (863 Program) (2003AA103510, 2004AA103130, 2005AA121210).
文摘A Single-Buffered （SB） router is a router where only one stage of shared buffering is sandwiched between two interconnects in comparison of a Combined Input and Output Queued （CIOQ） router where a central switch fabric is sandwiched between two stages of buffering. The notion of SB routers was firstly proposed by the High-Performance Networking Group （HPNG） of Stanford University, along with two promising designs of SB routers： one of which was Parallel Shared Memory （PSM） router and the other was Distributed Shared Memory （DSM） router. Admittedly, the work of HPNG deserved full credit, but all results presented by them appeared to relay on a Centralized Memory Management Algorithm （CMMA） which was essentially impractical because of the high processing and communication complexity. This paper attempts to make a scalable high-speed SB router completely practical by introducing a fully distributed architecture for managing the shared memory of SB routers. The resulting SB router is called as a Virtual Output and Input Queued （VOIQ） router. Furthermore, the scheme of VOIQ routers can not only eliminate the need for the CMMA scheduler, thus allowing a fully distributed implementation with low processing and commu- nication complexity, but also provide QoS guarantees and efficiently support variable-length packets in this paper. In particular, the results of performance testing and the hardware implementation of our VOIQ-based router （NDSC~ SR1880-TTM series） are illustrated at the end of this paper. The proposal of this paper is the first distributed scheme of how to design and implement SB routers publicized till now.
文摘In order to optimize the electricity yield of CSP （concentrated solar power） plants, TES （thermal energy storage） systems are regarded as an essential component. Furthermore, for many electricity grid operators, it is important to have spinning reserves in the grid and dispatchable power available, both offered by CSP-plants with integrated thermal energy storage. Enolcon is developing a new TES-system since several years. The system itself was designed to offer a principle simple and robust setup （with regard to execution and operation） and which is reducing the electricity costs of CSP-power plants by the consequent use of state of the art technology. Furthermore, such system shall be open to future developments of CSP-systems with regard to increasing steam temperatures and steam pressure. Such TES-system shall be commercially available for large scale application already in year 2014/2015. The key elements of the enolcon-TES are the open cycle using always ambient air with an air-air-heat exchanger and the arrangement of the storage material in such way to minimize the pressure losses and the own electricity consumption. The development is progressing in a structured way by studies, engineering works, TES-pilot plants, isothermal air flow test plant for the verification of the CFD-calculations, and since end of 2012 by the operation of a high temperature TES-module with all features of the large scale modules.
基金supported by National Natural Science Foundation of China (Grant No. 91230107)National Basic Research Program of China (973) (Grant No. 2013CBA01604)National High Technology Research and Development Program of China (863) (Grant No. 2015AA016501)
文摘This work presents a self-consistent two-dimensional(2-D) simulation method with unified physical models for different operation regimes of charge trapping memory. The simulation carefully takes into consideration the tunneling process, charge trapping/de-trapping mechanisms, and 2-D drift-diffusion transport within the storage layer. A string of three memory cells has been simulated and evaluated for different gate stack compositions and temperatures. The simulator is able to describe the charge transport behavior along bitline and tunneling directions under different operations. Good agreement has been made with experimental data,which hence validates the implemented physical models and altogether confirms the simulation as a valuable tool for evaluating the characteristics of three-dimensional NAND flash memory.
文摘Consistent high-quality and defect-free production is the demand of the day. The product recall not only increases engineering and manufacturing cost but also affects the quality and the reliability of the product in the eye of users. The monitoring and improvement of a manufacturing process are the strength of statistical process control. In this article we propose a process monitoring memory-based scheme for continuous data under the assumption of normality to detect small non-random shift patterns in any manufacturing or service process.The control limits for the proposed scheme are constructed. The in-control and out-of-control average run length(AVL) expressions have been derived for the performance evaluation of the proposed scheme. Robustness to non-normality has been tested after simulation study of the run length distribution of the proposed scheme, and the comparisons with Shewhart and exponentially weighted moving average(EWMA) schemes are presented for various gamma and t-distributions. The proposed scheme is effective and attractive as it has one design parameter which differentiates it from the traditional schemes. Finally, some suggestions and recommendations are made for the future work.
