With the increasing demand for flexible and efficient implementation of image and video processing algorithms, there should be a good tradeoff between hardware and software design method. This paper utilized the HW-SW...With the increasing demand for flexible and efficient implementation of image and video processing algorithms, there should be a good tradeoff between hardware and software design method. This paper utilized the HW-SW codesign method to implement the H.264 decoder in an SoC with an ARM core, a multimedia processor and a deblocking filter coprocessor. For the parallel processing features of the multimedia processor, clock cycles of decoding process can be dramatically reduced. And the hardware dedicated deblocking filter coprocessor can improve the efficiency a lot. With maximum clock frequency of 150 MHz, the whole system can achieve real time processing speed and flexibility.展开更多
Y2000-62092-Ⅳ-572 0011367高速卫星通信用的递归最大似然译码器=Recursivemaximum Iikelihood decoder for high-speed satellite com-munication[会,英]/Miki,M.H.& Taki,D.//1999IEEE International Symposium on Circuits and ...Y2000-62092-Ⅳ-572 0011367高速卫星通信用的递归最大似然译码器=Recursivemaximum Iikelihood decoder for high-speed satellite com-munication[会,英]/Miki,M.H.& Taki,D.//1999IEEE International Symposium on Circuits and Systems,Vol.4 of 6.—Ⅳ.572～575(PC)介绍了高速卫星通信专用的(64,35)里德-马勒子码译码器。利用加法-比较-选择(ACS)树3级流水线结构可在单片上完成基于格的递归最大似然译码算法,它大大减少了传统维特比算法的计算成本。展开更多
文摘With the increasing demand for flexible and efficient implementation of image and video processing algorithms, there should be a good tradeoff between hardware and software design method. This paper utilized the HW-SW codesign method to implement the H.264 decoder in an SoC with an ARM core, a multimedia processor and a deblocking filter coprocessor. For the parallel processing features of the multimedia processor, clock cycles of decoding process can be dramatically reduced. And the hardware dedicated deblocking filter coprocessor can improve the efficiency a lot. With maximum clock frequency of 150 MHz, the whole system can achieve real time processing speed and flexibility.
文摘Y2000-62092-Ⅳ-572 0011367高速卫星通信用的递归最大似然译码器=Recursivemaximum Iikelihood decoder for high-speed satellite com-munication[会,英]/Miki,M.H.& Taki,D.//1999IEEE International Symposium on Circuits and Systems,Vol.4 of 6.—Ⅳ.572～575(PC)介绍了高速卫星通信专用的(64,35)里德-马勒子码译码器。利用加法-比较-选择(ACS)树3级流水线结构可在单片上完成基于格的递归最大似然译码算法,它大大减少了传统维特比算法的计算成本。
