Recently a Hybrid Carrier (HC) scheme based on Weighted-type Fractional Fourier Transform (WFRFT) was proposed and developed, which contains Single Carrier (SC) and Multi-Carrier (MC) synergetie transmission. ...Recently a Hybrid Carrier (HC) scheme based on Weighted-type Fractional Fourier Transform (WFRFT) was proposed and developed, which contains Single Carrier (SC) and Multi-Carrier (MC) synergetie transmission. The wide interest is primarily due to its appealing characteristics, such as the robust performances in different types of selective fading channels and a great deal of potential for secure communications. According to the literatures, the HC signal and SC or MC signal probability distributions are different. In particular, some benefits of this HC scheme are brought by the quasi-Gaussian distribution of WFRFT signals. However, until now researchers have only presented statistic properties through computer simulations, and the accurate expressions of signals are not derived yet. In this paper, we derive the accu- rate and rigorously established closed-form expressions of Probability Density Function (PDF) of WFRFT signal real and imaginary parts with a large number of QPSK subcarriers, and this PDF can describe the behavior of data modulated by WFRFT, avoiding the complex computation for extensive computer simulations. Furthermore, the components of PDF expression are described and analyzed, and it is revealed that the tendency of signal quasi-Gaussian changes with the increasing of the parameter a (a in (0,1]). To validate the analytical results, extensive simulations have been conducted, showing a very good match between the analytical results and the real situations. The contribution of this paper may be useful to deduce the closed form expressions of Bit Error Ratio (BER), the Complementary Cumulative Distribution Function (CCDF) of Peak to Average Power Ratio (PAPR), and other analytical studies which adopt the PDF.展开更多
Estimation precision of Displaced Phase Center Algorithm(DPCA) is affected by the number of displaced phase center pairs,the bandwidth of transmitting signal and many other factors.Detailed analysis is made on DPCA...Estimation precision of Displaced Phase Center Algorithm(DPCA) is affected by the number of displaced phase center pairs,the bandwidth of transmitting signal and many other factors.Detailed analysis is made on DPCA's estimation precision.Analysis results show that the directional vector estimation precision of DPCA is low,which will produce accumulating errors when phase cen-ters' track is estimated.Because of this reason,DPCA suffers from accumulating errors seriously.To overcome this problem,a method combining DPCA with Sub Aperture Image Correlation(SAIC) is presented.Large synthetic aperture is divided into sub-apertures.Micro errors in sub-aperture are estimated by DPCA and compensated to raw echo data.Bulk errors between sub-apertures are esti-mated by SAIC and compensated directly to sub-aperture images.After that,sub-aperture images are directly used to generate ultimate SAS image.The method is applied to the lake-trial dataset of a 20 kHz SAS prototype system.Results show the method can successfully remove the accumulating error and produce a better SAS image.展开更多
We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic(CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multipli...We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic(CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multiplier is improved. The adiabatic two's complement multiplier-accumulator(MAC) is furthermore a design based on the CTGAL. The computer simulation results indicate that the designed circuit has the correct logic function and remarkably less energy consumption compared to that of the MAC based on complementary metal oxide semiconductor(CMOS) logic.展开更多
基金supported by the National Natural Science Foundation General Program of China(No.61201146)the National Basic Research Program of China(2013CB329003)the Fundamental Research Funds for the Central Universities(HIT.NSRIF.2015022)
文摘Recently a Hybrid Carrier (HC) scheme based on Weighted-type Fractional Fourier Transform (WFRFT) was proposed and developed, which contains Single Carrier (SC) and Multi-Carrier (MC) synergetie transmission. The wide interest is primarily due to its appealing characteristics, such as the robust performances in different types of selective fading channels and a great deal of potential for secure communications. According to the literatures, the HC signal and SC or MC signal probability distributions are different. In particular, some benefits of this HC scheme are brought by the quasi-Gaussian distribution of WFRFT signals. However, until now researchers have only presented statistic properties through computer simulations, and the accurate expressions of signals are not derived yet. In this paper, we derive the accu- rate and rigorously established closed-form expressions of Probability Density Function (PDF) of WFRFT signal real and imaginary parts with a large number of QPSK subcarriers, and this PDF can describe the behavior of data modulated by WFRFT, avoiding the complex computation for extensive computer simulations. Furthermore, the components of PDF expression are described and analyzed, and it is revealed that the tendency of signal quasi-Gaussian changes with the increasing of the parameter a (a in (0,1]). To validate the analytical results, extensive simulations have been conducted, showing a very good match between the analytical results and the real situations. The contribution of this paper may be useful to deduce the closed form expressions of Bit Error Ratio (BER), the Complementary Cumulative Distribution Function (CCDF) of Peak to Average Power Ratio (PAPR), and other analytical studies which adopt the PDF.
基金Supported by the National High Technology Research and Development Program of China (863 Program, 2007AA 091101)
文摘Estimation precision of Displaced Phase Center Algorithm(DPCA) is affected by the number of displaced phase center pairs,the bandwidth of transmitting signal and many other factors.Detailed analysis is made on DPCA's estimation precision.Analysis results show that the directional vector estimation precision of DPCA is low,which will produce accumulating errors when phase cen-ters' track is estimated.Because of this reason,DPCA suffers from accumulating errors seriously.To overcome this problem,a method combining DPCA with Sub Aperture Image Correlation(SAIC) is presented.Large synthetic aperture is divided into sub-apertures.Micro errors in sub-aperture are estimated by DPCA and compensated to raw echo data.Bulk errors between sub-apertures are esti-mated by SAIC and compensated directly to sub-aperture images.After that,sub-aperture images are directly used to generate ultimate SAS image.The method is applied to the lake-trial dataset of a 20 kHz SAS prototype system.Results show the method can successfully remove the accumulating error and produce a better SAS image.
基金supported by the National Natural Science Foundation of China (No. 60776022)the Science and Technology Fund of Zhejiang Province (No. 2008C21166)+3 种基金the Key Scientific Research Fund of the Department of Education of Zhejiang Province (No. 20061666)the Professor Fund (No. JSL2007001)the Scientific Research Fund (No. XK0610030)the K. C. Wong Magna Fund in Ningbo University, China
文摘We propose a new design scheme for a Booth encoder based on clocked transmission gate adiabatic logic(CTGAL). In the new design the structural complexity of the Booth encoder is reduced while the speed of the multiplier is improved. The adiabatic two's complement multiplier-accumulator(MAC) is furthermore a design based on the CTGAL. The computer simulation results indicate that the designed circuit has the correct logic function and remarkably less energy consumption compared to that of the MAC based on complementary metal oxide semiconductor(CMOS) logic.