Viterbi decoding is widely used in many radio systems. Because of the large computation complexity, it is usually implemented with ASIC chips, FPGA chips, or optimized hardware accelerators. With the rapid development...Viterbi decoding is widely used in many radio systems. Because of the large computation complexity, it is usually implemented with ASIC chips, FPGA chips, or optimized hardware accelerators. With the rapid development of the multicore technology, multicore platforms become a reasonable choice for software radio (SR) systems. The Cell Broadband Engine processor is a state-of-art multi-core processor designed by Sony, Toshiba, and IBM. In this paper, we present a 64-state soft input Viterbi decoder for WiMAX SR Baseband system based on the Cell processor. With one Synergistic Processor Element (SPE) of a Cell Processor running at 3.2GHz, our Viterbi decoder can achieve the throughput up to 30Mb/s to decode the tail-biting convolutional code. The performance demonstrates that the proposed Viterbi decoding implementation is very efficient. Moreover, the Viterbi decoder can be easily integrated to the SR system and can provide a highly integrated SR solution. The optimization methodology in this module design can be extended to other modules on Cell platform.展开更多
This paper presents an equalization algorithm for continuous phase modulation （CPM） over frequency-selective channels. A specific training sequence is first embedded in each data packet. By recursive least-squares ...This paper presents an equalization algorithm for continuous phase modulation （CPM） over frequency-selective channels. A specific training sequence is first embedded in each data packet. By recursive least-squares （RLS） estimation, the channel information parameters can be acquired, and a fractionally Simulation results show that the proposed algorithm can acquire the spaced equalizer performs joint decoding and equalization. channel information parameters rapidly and accurately, and that the fractionally spaced equalizer can eliminate the intersymbol interference （ISI） effectively, and is not sensitive to timing inaccuracy, so this algorithm can be exploited for demodulation system in burst mode.展开更多
文摘Viterbi decoding is widely used in many radio systems. Because of the large computation complexity, it is usually implemented with ASIC chips, FPGA chips, or optimized hardware accelerators. With the rapid development of the multicore technology, multicore platforms become a reasonable choice for software radio (SR) systems. The Cell Broadband Engine processor is a state-of-art multi-core processor designed by Sony, Toshiba, and IBM. In this paper, we present a 64-state soft input Viterbi decoder for WiMAX SR Baseband system based on the Cell processor. With one Synergistic Processor Element (SPE) of a Cell Processor running at 3.2GHz, our Viterbi decoder can achieve the throughput up to 30Mb/s to decode the tail-biting convolutional code. The performance demonstrates that the proposed Viterbi decoding implementation is very efficient. Moreover, the Viterbi decoder can be easily integrated to the SR system and can provide a highly integrated SR solution. The optimization methodology in this module design can be extended to other modules on Cell platform.
文摘This paper presents an equalization algorithm for continuous phase modulation （CPM） over frequency-selective channels. A specific training sequence is first embedded in each data packet. By recursive least-squares （RLS） estimation, the channel information parameters can be acquired, and a fractionally Simulation results show that the proposed algorithm can acquire the spaced equalizer performs joint decoding and equalization. channel information parameters rapidly and accurately, and that the fractionally spaced equalizer can eliminate the intersymbol interference （ISI） effectively, and is not sensitive to timing inaccuracy, so this algorithm can be exploited for demodulation system in burst mode.
