一种基于一体化信道的数据格式集成解译器设计

无人飞行器测控系统是直接关系飞行任务成败的关键系统,数据格式集成解译器则是飞行器与测控系统下行链路的接口。本文分析了飞行器的测控需求,为简化设备和节省频谱资源,在一体化信道的基础上对数据格式集成解译器进行了设计和仿真。

基于嵌入式SQL的Datalog演绎规则解释器的设计

文章提出了一个建立在传统关系数据库基础上的能支持ANSISQL与嵌入式SQL的演绎规则解释器。利用这个解释器,用户能够定义一个蕴含关系并可以像在演绎数据库中使用Datalog规则一样来提出查询。其方法是把演绎规则和查询翻译成嵌入式SQL程序,该程序在执行查询时能被调用。这个解释器可以被认为是扩充RDBMS演绎查询功能的一个前端工具。

基于生成对抗网络的高光谱影像解译算法

高光谱遥感能够获取蕴含着丰富地表覆盖信息的高光谱影像,在国民经济建设和国防军事信息化领域都有着广阔且深远的发展潜力。高光谱影像解译是其应用的核心技术之一。近年来,高光谱遥感系统不断提高的光谱分辨率和不断增加的成像设备量化深度使得获取的影像越来越精细,但同时也给解译任务带来诸多挑战。为解决基于深度学习的解译方法在小样本条件下容易过拟合及泛化能力差的问题,本文基于生成对抗网络,设计了一种用于高光谱影像解译的深度卷积生成对抗网络模型。该网络去除了全连接的隐藏层和池化层,其中,生成器采取微步卷积作为上采样策略,以随机噪声和样本的类别标签作为输入得到伪样本。判别器和解译器均采取步长卷积作为下采样策略,以生成的伪样本和真实的训练样本作为输入,以判别真伪和类别标签。训练中根据多解译损失优化参数,相较传统生成对抗网络,其能够更合理地优化损失函数,通过对抗性训练模型可学习到高光谱影像数据集的真实概率分布,并可根据学习到的代表性空谱特征对高光谱影像进行解译,解译精度高。

High Performance Viterbi Decoder on Cell/B.E.

Viterbi decoding is widely used in many radio systems. Because of the large computation complexity, it is usually implemented with ASIC chips, FPGA chips, or optimized hardware accelerators. With the rapid development of the multicore technology, multicore platforms become a reasonable choice for software radio (SR) systems. The Cell Broadband Engine processor is a state-of-art multi-core processor designed by Sony, Toshiba, and IBM. In this paper, we present a 64-state soft input Viterbi decoder for WiMAX SR Baseband system based on the Cell processor. With one Synergistic Processor Element (SPE) of a Cell Processor running at 3.2GHz, our Viterbi decoder can achieve the throughput up to 30Mb/s to decode the tail-biting convolutional code. The performance demonstrates that the proposed Viterbi decoding implementation is very efficient. Moreover, the Viterbi decoder can be easily integrated to the SR system and can provide a highly integrated SR solution. The optimization methodology in this module design can be extended to other modules on Cell platform.

An Iterative Decoding Scheme for Davey-MacKay Construction

In the Davey-MacKay(DM) construction,the inner decoder treats unknown transmitted bits as random independent substitution errors. It limits the synchronization capability of the inner decoder, and thus weakens the error-correcting capability of the DM construction.In order to improve the performance of the DM construction, an iterative decoding scheme is proposed, which iteratively utilizes the more accurate estimates of transmitted codewords. In the proposed scheme, the estimated average bit error rates and the estimated low-density parity-check(LDPC) codewords from the outer decoder are fed back into the inner decoder to update the synchronization process. Simulation results show that the proposed iterative decoding scheme significantly outperforms the traditional DM construction.

Scaling Factor Optimization of Turbo-Polar Iterative Decoding

In this paper, we investigate the weighted iterative decoding to improve the performance of turbo-polar code. First of all, a minimum weighted mean square error criterion is proposed to optimize the scaling factors(SFs). Secondly, for two typical iterative algorithms,such as soft cancellation(SCAN) and belief propagation(BP) decoding, genie-aided decoders are proposed as the ideal reference of the practical decoding. Guided by this optimization framework, the optimal SFs of SCAN or BP decoders are obtained. The bit error rate performance of turbo-polar code with the optimal SFs can achieve 0.3 dB or 0.7 dB performance gains over the standard SCAN or BP decoding respectively.

Design of a(480,240)CMOS Analog Low-Density Parity-Check Decoder

Digital low-density parity-check(LDPC) decoders can hardly meet the power-limits brought by the new application scenarios. The analog LDPC decoder, which is an application of the analog computation technology, is considered to have the potential to address this issue to some extent. However, due to the lack of automation tools and analog stopping criteria, the analog LDPC decoders suffer from costly handcraft design and additional decoding delay, and are not feasible to practical applications. To address these issues, a decoder architecture using reusable building blocks is designed to lower the handcraft design, and a probability stopping criterion that is specially designed for analog decoder is further planned and implemented to reduce the decoding delay. Then, a(480,240) CMOS analog LDPC decoder is designed and fabricated in a 0.35-μm CMOS technology. Experimental results show that the decoder prototype can achieve 50 Mbps throughput when the power consumption is about 86.3m W, and the decoding delay can be reduced by at most 93% compared with using the preset maximum decoding delay in existing works.

解析遥感图像解译专家系统运行机理

广义的遥感图像解译专家系统由图像处理与特征提取子系统、遥感图像解译知识获取系统,狭义的遥感图像解译专家系统三部分组成。重点介绍狭义的遥感图像解译专家系统的运行机理。狭义的遥感图像解译专家系统包括遥感图像数据库、解译知识库、推理机和解释器。这四部分各自独立又相互依赖,共同运作完成遥感图像的自动化解译。