The pore structure images of ore particles located at different heights of leaching column were scanned with X-ray computerized tomography (CT) scanner, the porosity and pore size distribution were calculated and the ...The pore structure images of ore particles located at different heights of leaching column were scanned with X-ray computerized tomography (CT) scanner, the porosity and pore size distribution were calculated and the geometrical shape and connectivity of pores were analyzed based on image process method, and the three dimensional reconstruction of pore structure images was realized. The results show that the porosity of ore particles bed in leaching column is 42.92%, 41.72%, 39.34% at top, middle and bottom zone, respectively. Obviously it has spatial variability and decreases appreciably along the height of the column. The overall average porosity obtained by image processing is 41.33% while the porosity gotten from general measurement method in laboratory is 42.77% showing the results of both methods are consistent well. The pore structure of ore granular media is characterized as a dynamical space network composed of interconnected pore bodies and pore throats. The ratio of throats with equivalent diameter less than 1.91 mm to the total pores is 29.31%, and that of the large pores with equivalent diameter more than 5.73 mm is 2.90%.展开更多
The 32-bit extensible embedded processor RISC3200 originating from an RTL prototype core is intended for low-cost consumer multimedia products. In order to incorporate the reduced instruction set and the multimedia ex...The 32-bit extensible embedded processor RISC3200 originating from an RTL prototype core is intended for low-cost consumer multimedia products. In order to incorporate the reduced instruction set and the multimedia extension instruction set in a unifying pipeline, a scalable super-pipeline technique is adopted. Several other optimization techniques are proposed to boost the frequency and reduce the average CPI of the unifying pipeline. Based on a data flow graph (DFG) with delay information, the critical path of the pipeline stage can be located and shortened. This paper presents a distributed data bypass unit and a centralized pipeline control scheme for achieving lower CPI. Synthesis and simulation showed that the optimization techniques enable RISC3200 to operate at 200 MHz with an average CPI of 1.16. The core was integrated into a media SOC chip taped out in SMIC 0.18-micron technology. Preliminary testing result showed that the processor works well as we expected.展开更多
Network processors are used in the core node of network to flexibly process packet streams. With the increase of performance, the power of network processor increases fast, and power and cooling become a bottleneck. A...Network processors are used in the core node of network to flexibly process packet streams. With the increase of performance, the power of network processor increases fast, and power and cooling become a bottleneck. Architecture-level power conscious design must go beyond low-level circuit design. Architectural power and performance tradeoff should be considered at the same time. Simulation is an efficient method to design modem network processor before making chip. In order to achieve the tradeoff between performance and power, the processor simulator is used to design the architecture of network processor. Using Netbeneh, Commubench benchmark and processor simulator-SimpleScalar, the performance and power of network processor are quantitatively evaluated. New performance tradeoff evaluation metric is proposed to analyze the architecture of network processor. Based on the high performance lnteI IXP 2800 Network processor eonfignration, optimized instruction fetch width and speed ,instruction issue width, instruction window size are analyzed and selected. Simulation resuits show that the tradeoff design method makes the usage of network processor more effectively. The optimal key parameters of network processor are important in architecture-level design. It is meaningful for the next generation network processor design.展开更多
Visual imagery constitutes the most important sensory information for humans.The entire field of acquiring,analyzing and synthesizing visual data by means of computers is called visual computing.It has an extraordinar...Visual imagery constitutes the most important sensory information for humans.The entire field of acquiring,analyzing and synthesizing visual data by means of computers is called visual computing.It has an extraordinarily wide range of applications,including for example:industrial quality control,street view and driver assistance systems,robot navigation,multimedia systems,and computer games.展开更多
基金Project(2004CB619205) supported by the National Key Fundamental Research and Development Program of ChinaProject(50325415) supported by the National Science Fund for Distinguished Young ScholarsProject(50574099) supported by the National Natural Science Foundation of China
文摘The pore structure images of ore particles located at different heights of leaching column were scanned with X-ray computerized tomography (CT) scanner, the porosity and pore size distribution were calculated and the geometrical shape and connectivity of pores were analyzed based on image process method, and the three dimensional reconstruction of pore structure images was realized. The results show that the porosity of ore particles bed in leaching column is 42.92%, 41.72%, 39.34% at top, middle and bottom zone, respectively. Obviously it has spatial variability and decreases appreciably along the height of the column. The overall average porosity obtained by image processing is 41.33% while the porosity gotten from general measurement method in laboratory is 42.77% showing the results of both methods are consistent well. The pore structure of ore granular media is characterized as a dynamical space network composed of interconnected pore bodies and pore throats. The ratio of throats with equivalent diameter less than 1.91 mm to the total pores is 29.31%, and that of the large pores with equivalent diameter more than 5.73 mm is 2.90%.
基金Project supported by the Hi-Tech Research and Development Pro-gram (863) of China (No. 2002 AA1Z1140) and the Fork Ying TongEducation Foundation (No. 94031), China
文摘The 32-bit extensible embedded processor RISC3200 originating from an RTL prototype core is intended for low-cost consumer multimedia products. In order to incorporate the reduced instruction set and the multimedia extension instruction set in a unifying pipeline, a scalable super-pipeline technique is adopted. Several other optimization techniques are proposed to boost the frequency and reduce the average CPI of the unifying pipeline. Based on a data flow graph (DFG) with delay information, the critical path of the pipeline stage can be located and shortened. This paper presents a distributed data bypass unit and a centralized pipeline control scheme for achieving lower CPI. Synthesis and simulation showed that the optimization techniques enable RISC3200 to operate at 200 MHz with an average CPI of 1.16. The core was integrated into a media SOC chip taped out in SMIC 0.18-micron technology. Preliminary testing result showed that the processor works well as we expected.
基金Sponsored by the National Defence Research Foundation of China(Grant No.413460303).
文摘Network processors are used in the core node of network to flexibly process packet streams. With the increase of performance, the power of network processor increases fast, and power and cooling become a bottleneck. Architecture-level power conscious design must go beyond low-level circuit design. Architectural power and performance tradeoff should be considered at the same time. Simulation is an efficient method to design modem network processor before making chip. In order to achieve the tradeoff between performance and power, the processor simulator is used to design the architecture of network processor. Using Netbeneh, Commubench benchmark and processor simulator-SimpleScalar, the performance and power of network processor are quantitatively evaluated. New performance tradeoff evaluation metric is proposed to analyze the architecture of network processor. Based on the high performance lnteI IXP 2800 Network processor eonfignration, optimized instruction fetch width and speed ,instruction issue width, instruction window size are analyzed and selected. Simulation resuits show that the tradeoff design method makes the usage of network processor more effectively. The optimal key parameters of network processor are important in architecture-level design. It is meaningful for the next generation network processor design.
文摘Visual imagery constitutes the most important sensory information for humans.The entire field of acquiring,analyzing and synthesizing visual data by means of computers is called visual computing.It has an extraordinarily wide range of applications,including for example:industrial quality control,street view and driver assistance systems,robot navigation,multimedia systems,and computer games.
