Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behav...Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behavioral level model(BLM) of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper,and the design of PLL based clock and data recovery(CDR)circuit aided with jitter attenuation PLL for SerDes application is also presented.The CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked loop.To simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network(ITU-T OTN),an additional jitter attenuation PLL is used.Simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17 ps and 2.3ps respectively.The core of the whole chip consumes 72 mA current from a 1.0V supply.展开更多
Tandem learning via email and computer-mediated communication activities flanked standard frontal English lessons for Italian adult learners in Italy. It is here suggested that the combination of tandem learning, vari...Tandem learning via email and computer-mediated communication activities flanked standard frontal English lessons for Italian adult learners in Italy. It is here suggested that the combination of tandem learning, various communication activities performed on-line, and standard courses help mature students to boost their self-esteem, give them more autonomy, and enhance their motivation. Tandem learning, which is based on the principles of reciprocity and autonomy, is ideally suited for adult students. It helps overcome the problems connected to the affective reactions of adults, and at the same time, being content driven, offers a more natural setting to learn an L2 （second language） on a mutual supportive basis.展开更多
Integer overflow vulnerability will cause buffer overflow. The research on the relationship between them will help us to detect integer overflow vulnerability. We present a dynamic analysis methods RICB （Run-time Int...Integer overflow vulnerability will cause buffer overflow. The research on the relationship between them will help us to detect integer overflow vulnerability. We present a dynamic analysis methods RICB （Run-time Integer Checking via Buffer overflow）. Our approach includes decompile execute file to assembly language; debug the execute file step into and step out; locate the overflow points and checking buffer overflow caused by integer overflow. We have implemented our approach in three buffer overflow types： format string overflow, stack overflow and heap overflow. Experiments results show that our approach is effective and efficient. We have detected more than 5 known integer overflow vulnerabilities via buffer overflow.展开更多
In order to provide power quality monitoring activities with metrological certification, a DAS （data acquisition system） has been designed, realized and characterized. The system allows acquisition on tri-phases plu...In order to provide power quality monitoring activities with metrological certification, a DAS （data acquisition system） has been designed, realized and characterized. The system allows acquisition on tri-phases plus neutral lines picking up 499 samples per period of the fundamental at 50 Hz. To ensure certified measurements, the system gets external certified time and voltage references. The system uses a FTDI Virtual Com Port Driver to communicate data over High Speed RS232 virtual interface and it does not need any advanced programming skill. The choice to use a virtual serial communication makes the data acquisition software portable over many platforms, regardless by the development environment and by the programming language. To test the proposed device some custom software have been written in many programming language （C^#, VB6, LabView, MatLab）, moreover in order to characterize the device the most common ADC （analog to digital converter） performing test have been applied.展开更多
基金Supported by the National High Technology Research and Development Programme of China(No.2011AA010301)the Research Foundation of Zhongxing Telecom Equipment Corporation and the National Natural Science Foundation of China(No.60976029)
文摘Phase locked loop(PLL) is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant.The behavioral level model(BLM) of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper,and the design of PLL based clock and data recovery(CDR)circuit aided with jitter attenuation PLL for SerDes application is also presented.The CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked loop.To simultaneously meet jitter tolerance and jitter transfer specifications defined in G.8251 of optical transport network(ITU-T OTN),an additional jitter attenuation PLL is used.Simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17 ps and 2.3ps respectively.The core of the whole chip consumes 72 mA current from a 1.0V supply.
文摘Tandem learning via email and computer-mediated communication activities flanked standard frontal English lessons for Italian adult learners in Italy. It is here suggested that the combination of tandem learning, various communication activities performed on-line, and standard courses help mature students to boost their self-esteem, give them more autonomy, and enhance their motivation. Tandem learning, which is based on the principles of reciprocity and autonomy, is ideally suited for adult students. It helps overcome the problems connected to the affective reactions of adults, and at the same time, being content driven, offers a more natural setting to learn an L2 （second language） on a mutual supportive basis.
基金Supported by the National Natural Science Foundation of China （60903188）, Shanghai Education Commission Innovation Foundation （11YZ192） and World Expo Science and Technology Special Fund of Shanghai Science and Technology Commission （08dz0580202）.
文摘Integer overflow vulnerability will cause buffer overflow. The research on the relationship between them will help us to detect integer overflow vulnerability. We present a dynamic analysis methods RICB （Run-time Integer Checking via Buffer overflow）. Our approach includes decompile execute file to assembly language; debug the execute file step into and step out; locate the overflow points and checking buffer overflow caused by integer overflow. We have implemented our approach in three buffer overflow types： format string overflow, stack overflow and heap overflow. Experiments results show that our approach is effective and efficient. We have detected more than 5 known integer overflow vulnerabilities via buffer overflow.
文摘In order to provide power quality monitoring activities with metrological certification, a DAS （data acquisition system） has been designed, realized and characterized. The system allows acquisition on tri-phases plus neutral lines picking up 499 samples per period of the fundamental at 50 Hz. To ensure certified measurements, the system gets external certified time and voltage references. The system uses a FTDI Virtual Com Port Driver to communicate data over High Speed RS232 virtual interface and it does not need any advanced programming skill. The choice to use a virtual serial communication makes the data acquisition software portable over many platforms, regardless by the development environment and by the programming language. To test the proposed device some custom software have been written in many programming language （C^#, VB6, LabView, MatLab）, moreover in order to characterize the device the most common ADC （analog to digital converter） performing test have been applied.
