We investigate a spin-to-charge conversion mechanism which maps the spin singlet and triplet states to two charge states differing by one electron mediated by an intermediate metastable charge state. This mechanism al...We investigate a spin-to-charge conversion mechanism which maps the spin singlet and triplet states to two charge states differing by one electron mediated by an intermediate metastable charge state. This mechanism allows us to observe fringes in the spin-unblocked region beyond the triplet transition line in the measurement of the exchange oscillations between singlet and triplet states in a four-electron dou- ble quantum dot. Moreover, these fringes are amplified and π-phase shifted, compared with those in the spin blockade region. Unlike the signal enhancement mechanism reported before which produces similar effects, this mechanism only requires one dot coupling to the lead, which is a commonly encountered case especially in imperfect devices. Besides, the crucial tunnel rate asymmetry is provided by the dependence on spin state, not by the asymmetric couplings to the leads. We also design a scheme to control the amplification process, which enables us to extract the relevant time parameters. This mechanism will have potential applications in future investigations of spin qubits.展开更多
A multi-stage dual replica bit-line delay （MDRBD） technique is proposed for reducing access time by suppressing the sense-amplifier enable （SAE） timing variation of low voltage static randomaccess memory （SRAM） ...A multi-stage dual replica bit-line delay （MDRBD） technique is proposed for reducing access time by suppressing the sense-amplifier enable （SAE） timing variation of low voltage static randomaccess memory （SRAM） applications. Compared with the traditional technique, this strategy, using statistical theory, reduces the timing variation by using multi-stage ideas, meanwhile doubling the replica bit-fine （RBL） capacitance and discharge path simultaneously in each stage. At a supply voltage of 0.6 V, the simulation results show that the standard deviations of the SAE timing and cycle time with the proposed technique are 69.2% and 47.2%, respectively, smaller than that with a conventional RBL delay technique in TSMC 65 nm CMOS technology （Taiwan Semiconductor Manufacturing Company, Taiwan）.展开更多
基金supported by the National Key Research and Development Program (2016YFA0301700)the National Natural Science Foundation of China (11674300, 11304301, 11575172,61674132, and 91421303)+2 种基金the Strategic Priority Research Program of Chinese Academy of Sciences (XDB01030000)the Fundamental Research Fund for the Central UniversitiesThis work was partially carried out at the USTC Center for Micro and Nanoscale Research and Fabrication
文摘We investigate a spin-to-charge conversion mechanism which maps the spin singlet and triplet states to two charge states differing by one electron mediated by an intermediate metastable charge state. This mechanism allows us to observe fringes in the spin-unblocked region beyond the triplet transition line in the measurement of the exchange oscillations between singlet and triplet states in a four-electron dou- ble quantum dot. Moreover, these fringes are amplified and π-phase shifted, compared with those in the spin blockade region. Unlike the signal enhancement mechanism reported before which produces similar effects, this mechanism only requires one dot coupling to the lead, which is a commonly encountered case especially in imperfect devices. Besides, the crucial tunnel rate asymmetry is provided by the dependence on spin state, not by the asymmetric couplings to the leads. We also design a scheme to control the amplification process, which enables us to extract the relevant time parameters. This mechanism will have potential applications in future investigations of spin qubits.
基金Project supported by the National Natural Science Foundation of China （No. 61474001）
文摘A multi-stage dual replica bit-line delay （MDRBD） technique is proposed for reducing access time by suppressing the sense-amplifier enable （SAE） timing variation of low voltage static randomaccess memory （SRAM） applications. Compared with the traditional technique, this strategy, using statistical theory, reduces the timing variation by using multi-stage ideas, meanwhile doubling the replica bit-fine （RBL） capacitance and discharge path simultaneously in each stage. At a supply voltage of 0.6 V, the simulation results show that the standard deviations of the SAE timing and cycle time with the proposed technique are 69.2% and 47.2%, respectively, smaller than that with a conventional RBL delay technique in TSMC 65 nm CMOS technology （Taiwan Semiconductor Manufacturing Company, Taiwan）.
