To minimize the power consumption with resources operating at multiple voltages a time-constrained algorithm is presented.The input to the scheme is an unscheduled data flow graph (DFG),and timing or resource constrai...To minimize the power consumption with resources operating at multiple voltages a time-constrained algorithm is presented.The input to the scheme is an unscheduled data flow graph (DFG),and timing or resource constraints.Partitioning is considered with scheduling in the proposed algorithm as multiple voltage design can lead to an increase in interconnection complexity at layout level.That is,in the proposed algorithm power consumption is first reduced by the scheduling step,and then the partitioning step takes over to decrease the interconnection complexity.The time-constrained algorithm has time complexity of O(n 2),where n is the number of nodes in the DFG.Experiments with a number of DSP benchmarks show that the proposed algorithm achieves the power reduction under timing constraints by an average of 46 5%.展开更多
In the traditional three-level space vector pulse width modulation(SVPWM)algorithm,the sector judgment is computationallycomplex since the sector is divided into triangles and hexagons.In addition,the switching freque...In the traditional three-level space vector pulse width modulation(SVPWM)algorithm,the sector judgment is computationallycomplex since the sector is divided into triangles and hexagons.In addition,the switching frequency is high becausethe seven-segment switching sequence is adopted.For this reason,a new SVPWM control algorithm for three-level inverteris proposed,in which the sector judgment is simplified by dividing the sector into quasi hexagons?and the new four-segmentswitching sequence is adopted to reduce the switching frequency.Simulation results show that the total harmonic distortiongrows down with the switching frequency decreasing,moreover,the algorithm runtime is also decreased.展开更多
文摘To minimize the power consumption with resources operating at multiple voltages a time-constrained algorithm is presented.The input to the scheme is an unscheduled data flow graph (DFG),and timing or resource constraints.Partitioning is considered with scheduling in the proposed algorithm as multiple voltage design can lead to an increase in interconnection complexity at layout level.That is,in the proposed algorithm power consumption is first reduced by the scheduling step,and then the partitioning step takes over to decrease the interconnection complexity.The time-constrained algorithm has time complexity of O(n 2),where n is the number of nodes in the DFG.Experiments with a number of DSP benchmarks show that the proposed algorithm achieves the power reduction under timing constraints by an average of 46 5%.
基金National Natural Science Foundation of China(No.61261029)
文摘In the traditional three-level space vector pulse width modulation(SVPWM)algorithm,the sector judgment is computationallycomplex since the sector is divided into triangles and hexagons.In addition,the switching frequency is high becausethe seven-segment switching sequence is adopted.For this reason,a new SVPWM control algorithm for three-level inverteris proposed,in which the sector judgment is simplified by dividing the sector into quasi hexagons?and the new four-segmentswitching sequence is adopted to reduce the switching frequency.Simulation results show that the total harmonic distortiongrows down with the switching frequency decreasing,moreover,the algorithm runtime is also decreased.
