This paper introduces the design of doubly fed system for conveyor belt motor, the system adopts stator flux orientation vector control technology and AC-AC inverter motor speed and power factor control, and carried o...This paper introduces the design of doubly fed system for conveyor belt motor, the system adopts stator flux orientation vector control technology and AC-AC inverter motor speed and power factor control, and carried on the test in transmission field. This paper introduces in detail the structure and characteristic of DSP system, and gives a design scheme of Doubly Fed Speed Control System of motor based on this chip.展开更多
To solve the issue of downloading speed and application scenarios limitation of current JTAGLink debugger, this paper presents a new scheme of ARM debugger with the feature of Ethemet interface implemented by pure har...To solve the issue of downloading speed and application scenarios limitation of current JTAGLink debugger, this paper presents a new scheme of ARM debugger with the feature of Ethemet interface implemented by pure hardware logic design. This paper outlines the principle of the scheme, blocks of logic design, and protocols design. The scheme provides higher downloading speed, wider flexibility on application, and improves work efficiency evidently. Key words: JTAGLink Debugger; Ethernet; FPGA; Logic Design展开更多
文摘This paper introduces the design of doubly fed system for conveyor belt motor, the system adopts stator flux orientation vector control technology and AC-AC inverter motor speed and power factor control, and carried on the test in transmission field. This paper introduces in detail the structure and characteristic of DSP system, and gives a design scheme of Doubly Fed Speed Control System of motor based on this chip.
文摘To solve the issue of downloading speed and application scenarios limitation of current JTAGLink debugger, this paper presents a new scheme of ARM debugger with the feature of Ethemet interface implemented by pure hardware logic design. This paper outlines the principle of the scheme, blocks of logic design, and protocols design. The scheme provides higher downloading speed, wider flexibility on application, and improves work efficiency evidently. Key words: JTAGLink Debugger; Ethernet; FPGA; Logic Design