A novel general-purpose low-voltage rail-to-rail CMOS （ complementary metal-oxide-semiconductor transistor ） operational amplifier （op-amp）is introduced, which obtains constant transconductance, slew rate and cons...A novel general-purpose low-voltage rail-to-rail CMOS （ complementary metal-oxide-semiconductor transistor ） operational amplifier （op-amp）is introduced, which obtains constant transconductance, slew rate and constant high gain over the entire input common mode voltage range. The proposed scheme has the potential for applications in deep submicrometer technology, as the operation of the circuit does not exclusively rely on the square-law or the linear-law of transistors. The scheme is compact and suitable for applications as VLSI cell. The rail-to- rail op-amp has been implemented in DPDM 0. 6 μm mixedsignal process. The simulations show that in the entire range of input common mode voltage, the variations in transconductance, SR and gain are 1%, 2. 3%, 1.36 dB, respectively. Based on this, the layout and tape-out are carded out. The area of layout is 0. 072 mm^2. The test results are basically consistent with the circuit simulation.展开更多
A design of a linear and fully-balanced operational transconductanee amplifier （OTA） with improved high DC gain and wide bandwidth is presented. Derivative from a single common-source field effect transistor （FET）...A design of a linear and fully-balanced operational transconductanee amplifier （OTA） with improved high DC gain and wide bandwidth is presented. Derivative from a single common-source field effect transistor （FET） cas- cade and its DC I-V characteristics,the third-order coefficient g3 hasbeen well compensated with a parallel FET operated in the triode region, which has even-odd symmetries between the boundary of the saturation and triode region. Therefore,for high linearity,a simple solution is obtained to increase input signal amplitude in saturation for the application of OTA continuous-time filters. A negative resistance load （NRL） technique is used for the compensation of parasitic output resistance and an achievement of a high DC-gain of the OTA circuits without extra internal nodes. Additionally, derivations from the ideal -90° phase of the gm-C integrator mainly due to a finite DC gain and parasitic poles will be avoided in the frequency range of interest. HSPICE simulation shows that the total harmonic distortion at 1Vp-p is less than 1% from a single 3.3V supply. As an application of the VHF CMOS OTA,a second-order OTA-C bandpass filter is fabricated using a 0. 18μm CMOS process with two kinds of gate-oxide layers, which has achieved a center frequency of 20MHz,a 3dB-bandwidth of 180kHz,and a quality factor of 110.展开更多
This paper describes the design and analysis of a fully differential,gain-enhanced CMOS telescopic operational transconductance amplifier （OTA） used in a pipeline analog-to-digital converter （ADC）. Specifications ...This paper describes the design and analysis of a fully differential,gain-enhanced CMOS telescopic operational transconductance amplifier （OTA） used in a pipeline analog-to-digital converter （ADC）. Specifications of the OTA are derived from the requirements of ADC. Simulation shows that for a lpF load capacitance, this OTA achieves a high DC gain （approximately 145dB） and a wide unity-gain bandwidth （above 750MHz） at a phase margin 58°. In a configuration where the closed loop-gain is 4,the design spends about 18ns for settling with 0.05% accuracy. Simulations of this design are performed in SMIC CMOS 0.18μm technology.展开更多
文摘A novel general-purpose low-voltage rail-to-rail CMOS （ complementary metal-oxide-semiconductor transistor ） operational amplifier （op-amp）is introduced, which obtains constant transconductance, slew rate and constant high gain over the entire input common mode voltage range. The proposed scheme has the potential for applications in deep submicrometer technology, as the operation of the circuit does not exclusively rely on the square-law or the linear-law of transistors. The scheme is compact and suitable for applications as VLSI cell. The rail-to- rail op-amp has been implemented in DPDM 0. 6 μm mixedsignal process. The simulations show that in the entire range of input common mode voltage, the variations in transconductance, SR and gain are 1%, 2. 3%, 1.36 dB, respectively. Based on this, the layout and tape-out are carded out. The area of layout is 0. 072 mm^2. The test results are basically consistent with the circuit simulation.
文摘A design of a linear and fully-balanced operational transconductanee amplifier （OTA） with improved high DC gain and wide bandwidth is presented. Derivative from a single common-source field effect transistor （FET） cas- cade and its DC I-V characteristics,the third-order coefficient g3 hasbeen well compensated with a parallel FET operated in the triode region, which has even-odd symmetries between the boundary of the saturation and triode region. Therefore,for high linearity,a simple solution is obtained to increase input signal amplitude in saturation for the application of OTA continuous-time filters. A negative resistance load （NRL） technique is used for the compensation of parasitic output resistance and an achievement of a high DC-gain of the OTA circuits without extra internal nodes. Additionally, derivations from the ideal -90° phase of the gm-C integrator mainly due to a finite DC gain and parasitic poles will be avoided in the frequency range of interest. HSPICE simulation shows that the total harmonic distortion at 1Vp-p is less than 1% from a single 3.3V supply. As an application of the VHF CMOS OTA,a second-order OTA-C bandpass filter is fabricated using a 0. 18μm CMOS process with two kinds of gate-oxide layers, which has achieved a center frequency of 20MHz,a 3dB-bandwidth of 180kHz,and a quality factor of 110.
文摘This paper describes the design and analysis of a fully differential,gain-enhanced CMOS telescopic operational transconductance amplifier （OTA） used in a pipeline analog-to-digital converter （ADC）. Specifications of the OTA are derived from the requirements of ADC. Simulation shows that for a lpF load capacitance, this OTA achieves a high DC gain （approximately 145dB） and a wide unity-gain bandwidth （above 750MHz） at a phase margin 58°. In a configuration where the closed loop-gain is 4,the design spends about 18ns for settling with 0.05% accuracy. Simulations of this design are performed in SMIC CMOS 0.18μm technology.
