本文介绍的4种新型数据转换器集成电路：ADC083000、AD7980、MAX1302、LTC2641。数据转换器包括ADC和DAC两大类，ADC是“Analog to Digital Converters”的缩写，中文名称是模数转换器，DAC是“Digital to Analog Converters”的缩写，...本文介绍的4种新型数据转换器集成电路：ADC083000、AD7980、MAX1302、LTC2641。数据转换器包括ADC和DAC两大类，ADC是“Analog to Digital Converters”的缩写，中文名称是模数转换器，DAC是“Digital to Analog Converters”的缩写，中文名称是数模转换器，此处的“数”是指“数字信号”，“模”是指“模拟信号”。我们已经开始进入数字化时代，数字化技术使参量的存储、处理、还原、转化、借用变得非常容易且不易产生额外的失真，不过通常我们所能感知的参量都是模拟的，如声音、图像、光线、温度、疼痛、压力、气味等，数据转换器在模拟与数字之间的转换起着重要的桥梁作用。实际的应用系统中，为了将模拟量转化为数字量，传感器是必须的，如数码相机中的CCD器件，温度传感器、压力传感器等；为了将数字量转化为模拟量，最终模拟执行机构也是必须的，大多根据实际用途来命名，如荧光屏是显示图像的，扬声器是发出声音的，继电器用作开关，这些器件作为一个系统的执行机构，将数字信息变为我们可以实际感知的信息——模拟参量。展开更多
High performance 1 57μm spotsize converter monolithically integrated DFB is fabricated by the technique of self aligned selective area growth.The upper optical confinement layer and the butt coupled tapered thickn...High performance 1 57μm spotsize converter monolithically integrated DFB is fabricated by the technique of self aligned selective area growth.The upper optical confinement layer and the butt coupled tapered thickness waveguide are regrown simultaneously,which not only offeres the separated optimization of the active region and the integrated spotsize converter,but also reduces the difficulty of the butt joint selective regrowth.The threshold current is as low as 4 4mA.The output power at 49mA is 10 1mW.The side mode suppression ratio (SMSR) is 33 2dB.The vertical and horizontal far field divergence angles are as small as 9° and 15° respectively,the 1dB misalignment tolerance are 3 6μm and 3 4μm.展开更多
The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double...The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double Centro symmetric current matrix is designed by the Q2 random walk strategy.To achieve better dynamic performance,a latch is added in front of the current switch to change the input signal,such as its optimal cross-point and voltage level.For a 12bit resolution,the converter reaches an update rate of 300MHz.展开更多
A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented witho...A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.展开更多
A novel 1 55μm laser diode with spot size converter is designed and fabricated using conventional photolithography and chemical wet etching process.For the laser diode,a ridge double core structure is employed.For...A novel 1 55μm laser diode with spot size converter is designed and fabricated using conventional photolithography and chemical wet etching process.For the laser diode,a ridge double core structure is employed.For the spot size converter,a buried ridge double core structure is incorporated.The laterally tapered active core is designed and optically combined with the thin and wide passive core to control the size of mode.The laser diode threshold current is measured to be 40mA together with high slop efficiency of 0 35W/A.The beam divergence angles in the horizontal and vertical directions are as small as 14 89°×18 18°,respectively,resulting in low coupling losses with a cleaved optical fiber (3dB loss).展开更多
A 1.60μm laser diode and electroabsorption modulator monolithically integrated with a novel dual-waveguide spot-size converter output for low-loss coupling to a cleaved single-mode optical fiber are demonstrated.The ...A 1.60μm laser diode and electroabsorption modulator monolithically integrated with a novel dual-waveguide spot-size converter output for low-loss coupling to a cleaved single-mode optical fiber are demonstrated.The devices emit in a single transverse and quasi single longitudinal mode with an SMSR of 25.6dB.These devices exhibit a 3dB modulation bandwidth of 15.0GHz,and modulator DC extinction ratios of 16.2dB.The output beam divergence angles of the spot-size converter in the horizontal and vertical directions are as small as 7.3°×18.0°,respectively,resulting in a 3.0dB coupling loss with a cleaved single-mode optical fiber.展开更多
This paper presents a 2GS/s 10bit CMOS digital-to-analog converter （DAC） that consists of two unit current-cell matrixes for 6MSBs and 4LSBs, respectively, trading off between the precision and size of the chip. Cur...This paper presents a 2GS/s 10bit CMOS digital-to-analog converter （DAC） that consists of two unit current-cell matrixes for 6MSBs and 4LSBs, respectively, trading off between the precision and size of the chip. Current mode logic （CML） is used to ensure high speed,and a double centro-symmetric current matrix is designed by the Q^2 random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2mm × 2.2mm of die area and consumes 790mW with a single 3.3V power supply.展开更多
With the increasing use of low voltage portable devices and wireless systems, energy harvesting has become an attractive approach to overcome the problems associated with battery life and power source. Among the diffe...With the increasing use of low voltage portable devices and wireless systems, energy harvesting has become an attractive approach to overcome the problems associated with battery life and power source. Among the different types of microenergy scavengers, the TEG （thermoelectric generators） are one of the most commonly used one. Unfortunately, due to the very small amount of voltage delivered by the TEG, an efficient DC/DC （direct current/direct current） conversion and power management techniques are needed. In this paper, a CMOS （complementary metal oxide semiconductor） fully-integrated DC/DC convener for energy harvesting applications is presented. The startup-voltage of the converter is about 140 mV, the output voltage exceeds 1.5 V, with a 20% power efficiency at least. The architecture for boosting such extremely low voltages is based on an ultra-low-voltage oscillator cross connected to two phase charge pump. The overall circuit does not require any external components and can be fully integrated in a standard CMOS low voltage technology. A test-chip has been designed in UMC （united microelectronics corporation） 180 nm CMOS process.展开更多
The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）,...The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）, negative word-line voltage （VinyL） and half-VDD voltage （VHDo） generator. To generate a process voltage temperature （PVT）-insensitive VpWL and VNWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a VOWL regulator and a VNWL charge pump were proposed for a small-area and low-power design. The proposed VpwL regulator can provide a large driving current with a small area since it regulates an input voltage （VCI） from 2.5 to 3.3 V. The VmvL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to VNWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.展开更多
文摘本文介绍的4种新型数据转换器集成电路：ADC083000、AD7980、MAX1302、LTC2641。数据转换器包括ADC和DAC两大类，ADC是“Analog to Digital Converters”的缩写，中文名称是模数转换器，DAC是“Digital to Analog Converters”的缩写，中文名称是数模转换器，此处的“数”是指“数字信号”，“模”是指“模拟信号”。我们已经开始进入数字化时代，数字化技术使参量的存储、处理、还原、转化、借用变得非常容易且不易产生额外的失真，不过通常我们所能感知的参量都是模拟的，如声音、图像、光线、温度、疼痛、压力、气味等，数据转换器在模拟与数字之间的转换起着重要的桥梁作用。实际的应用系统中，为了将模拟量转化为数字量，传感器是必须的，如数码相机中的CCD器件，温度传感器、压力传感器等；为了将数字量转化为模拟量，最终模拟执行机构也是必须的，大多根据实际用途来命名，如荧光屏是显示图像的，扬声器是发出声音的，继电器用作开关，这些器件作为一个系统的执行机构，将数字信息变为我们可以实际感知的信息——模拟参量。
文摘High performance 1 57μm spotsize converter monolithically integrated DFB is fabricated by the technique of self aligned selective area growth.The upper optical confinement layer and the butt coupled tapered thickness waveguide are regrown simultaneously,which not only offeres the separated optimization of the active region and the integrated spotsize converter,but also reduces the difficulty of the butt joint selective regrowth.The threshold current is as low as 4 4mA.The output power at 49mA is 10 1mW.The side mode suppression ratio (SMSR) is 33 2dB.The vertical and horizontal far field divergence angles are as small as 9° and 15° respectively,the 1dB misalignment tolerance are 3 6μm and 3 4μm.
文摘The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double Centro symmetric current matrix is designed by the Q2 random walk strategy.To achieve better dynamic performance,a latch is added in front of the current switch to change the input signal,such as its optimal cross-point and voltage level.For a 12bit resolution,the converter reaches an update rate of 300MHz.
文摘A CMOS folding and interpolating analog-to-digital converter (ADC) for embedded application is described.The circuit is fully compatible with standard digital CMOS technology.A modified folding block implemented without resistor contributes to a small chip area.At the input stage,offset averaging reduces the input capacitance and the distributed track-and-hold circuits are proposed to improve signal-to-noise-plus-distortion ratio.The 200Ms/s 8bit ADC with 177mW total power consumption at 3.3V power supply is realized in standard digital 0.18μm 3.3V CMOS technology.
文摘A novel 1 55μm laser diode with spot size converter is designed and fabricated using conventional photolithography and chemical wet etching process.For the laser diode,a ridge double core structure is employed.For the spot size converter,a buried ridge double core structure is incorporated.The laterally tapered active core is designed and optically combined with the thin and wide passive core to control the size of mode.The laser diode threshold current is measured to be 40mA together with high slop efficiency of 0 35W/A.The beam divergence angles in the horizontal and vertical directions are as small as 14 89°×18 18°,respectively,resulting in low coupling losses with a cleaved optical fiber (3dB loss).
文摘A 1.60μm laser diode and electroabsorption modulator monolithically integrated with a novel dual-waveguide spot-size converter output for low-loss coupling to a cleaved single-mode optical fiber are demonstrated.The devices emit in a single transverse and quasi single longitudinal mode with an SMSR of 25.6dB.These devices exhibit a 3dB modulation bandwidth of 15.0GHz,and modulator DC extinction ratios of 16.2dB.The output beam divergence angles of the spot-size converter in the horizontal and vertical directions are as small as 7.3°×18.0°,respectively,resulting in a 3.0dB coupling loss with a cleaved single-mode optical fiber.
文摘This paper presents a 2GS/s 10bit CMOS digital-to-analog converter （DAC） that consists of two unit current-cell matrixes for 6MSBs and 4LSBs, respectively, trading off between the precision and size of the chip. Current mode logic （CML） is used to ensure high speed,and a double centro-symmetric current matrix is designed by the Q^2 random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2mm × 2.2mm of die area and consumes 790mW with a single 3.3V power supply.
文摘With the increasing use of low voltage portable devices and wireless systems, energy harvesting has become an attractive approach to overcome the problems associated with battery life and power source. Among the different types of microenergy scavengers, the TEG （thermoelectric generators） are one of the most commonly used one. Unfortunately, due to the very small amount of voltage delivered by the TEG, an efficient DC/DC （direct current/direct current） conversion and power management techniques are needed. In this paper, a CMOS （complementary metal oxide semiconductor） fully-integrated DC/DC convener for energy harvesting applications is presented. The startup-voltage of the converter is about 140 mV, the output voltage exceeds 1.5 V, with a 20% power efficiency at least. The architecture for boosting such extremely low voltages is based on an ultra-low-voltage oscillator cross connected to two phase charge pump. The overall circuit does not require any external components and can be fully integrated in a standard CMOS low voltage technology. A test-chip has been designed in UMC （united microelectronics corporation） 180 nm CMOS process.
基金supported by the Second Stage of Brain Korea 21 Projectsfinancially supported by Changwon National University in 2011-2013
文摘The direct current-direct current （DC-DC） converter is designed for 1 T static random access memory （SRAM） used in display driver integrated circuits （ICs）, which consists of positive word-line voltage （VpwL）, negative word-line voltage （VinyL） and half-VDD voltage （VHDo） generator. To generate a process voltage temperature （PVT）-insensitive VpWL and VNWL, a set of circuits were proposed to generate reference voltages using bandgap reference current generators for respective voltage level detectors. Also, a VOWL regulator and a VNWL charge pump were proposed for a small-area and low-power design. The proposed VpwL regulator can provide a large driving current with a small area since it regulates an input voltage （VCI） from 2.5 to 3.3 V. The VmvL charge pump can be implemented as a high-efficiency circuit with a small area and low power since it can transfer pumped charges to VNWL node entirely. The DC-DC converter for 1 T SRAM were designed with 0.11 μm mixed signal process and operated well with satisfactory measurement results.
