The data information transfer and time marching strategies between computational fluid dynamics （CFD） and computational structural dynamics （CSD） play crucial roles on the aeroelastic analysis in a time domain. An...The data information transfer and time marching strategies between computational fluid dynamics （CFD） and computational structural dynamics （CSD） play crucial roles on the aeroelastic analysis in a time domain. An improved CFD/CSD coupled system is designed, including an interpolation method and an improved loosely coupled algorithm. The interpolation method based on boundary element method （BEM） is developed to transfer aerodynamic loads and structural displacements between CFD and CSD grid systems, it can be universally used in fluid structural interaction solution by keeping energy conservation. The improved loosely coupled algo-rithm is designed, thus it improves the computational accuracy and efficiency. The new interface is performed on the two-dimensional （2-D） extrapolation and the aeroelastie response of AGARD445.6 wing. Results show that the improved interface has a superior accuracy.展开更多
The paper proposes a novel zero current transition (ZCT) push pull forward converter. The auxiliary resonant cell is in parallel with the main circuit and the zero current switching (ZCS) range of the main and the aux...The paper proposes a novel zero current transition (ZCT) push pull forward converter. The auxiliary resonant cell is in parallel with the main circuit and the zero current switching (ZCS) range of the main and the auxiliary switches of the proposed converter are entirely achieved. The resonant capacitor achieves high voltage by operating the auxiliary cell. The auxiliary switch turns on before the main switches turn off, the high voltage of resonant capacitor blanks off the rectifier, and then the curr...展开更多
A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and ...A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.展开更多
A current-mode DC-DC buck converter with high stability is presented. The loop gain＇s expression of the current-mode converter is derived by employing an advanced model of a current-mode control converter. After anal...A current-mode DC-DC buck converter with high stability is presented. The loop gain＇s expression of the current-mode converter is derived by employing an advanced model of a current-mode control converter. After analyzing the loop gain＇s expression, which illustrates the method of selecting suitable frequency compensation for the control loop,a novel pole-zero tracking frequency compensation is proposed. Based on theoretical analysis, a DC-DC buck converter with high stability is designed with 0.5μm-CMOS technology. The simulated results reveal that the stability of the converter is independent of the load current and the input voltage. Moreover,the converter provides a full load transient response setting time of less than 5μs and overshoots and undershoots of less than 30mV.展开更多
The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double...The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double Centro symmetric current matrix is designed by the Q2 random walk strategy.To achieve better dynamic performance,a latch is added in front of the current switch to change the input signal,such as its optimal cross-point and voltage level.For a 12bit resolution,the converter reaches an update rate of 300MHz.展开更多
基金Supported by the Ph.D.Program Foundation of Ministry of Education of China (20070699054)~~
文摘The data information transfer and time marching strategies between computational fluid dynamics （CFD） and computational structural dynamics （CSD） play crucial roles on the aeroelastic analysis in a time domain. An improved CFD/CSD coupled system is designed, including an interpolation method and an improved loosely coupled algorithm. The interpolation method based on boundary element method （BEM） is developed to transfer aerodynamic loads and structural displacements between CFD and CSD grid systems, it can be universally used in fluid structural interaction solution by keeping energy conservation. The improved loosely coupled algo-rithm is designed, thus it improves the computational accuracy and efficiency. The new interface is performed on the two-dimensional （2-D） extrapolation and the aeroelastie response of AGARD445.6 wing. Results show that the improved interface has a superior accuracy.
文摘The paper proposes a novel zero current transition (ZCT) push pull forward converter. The auxiliary resonant cell is in parallel with the main circuit and the zero current switching (ZCS) range of the main and the auxiliary switches of the proposed converter are entirely achieved. The resonant capacitor achieves high voltage by operating the auxiliary cell. The auxiliary switch turns on before the main switches turn off, the high voltage of resonant capacitor blanks off the rectifier, and then the curr...
文摘A 1.8V 8b 125Msample/s pipelined A/D converter is presented.Power efficiency is optimized by size scaling down scheme using low power single stage cascode amplifier with a gain boosted structure.Global clock tree and local generators are employed to avoid loss and overlap of clock period.The ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 49.5dB(7.9ENOB) for an input of 62MHz at full speed of 125MHz,consuming only 71mW.It is implemented in 0.18μm CMOS technology with a core area of 0.45mm 2.
文摘A current-mode DC-DC buck converter with high stability is presented. The loop gain＇s expression of the current-mode converter is derived by employing an advanced model of a current-mode control converter. After analyzing the loop gain＇s expression, which illustrates the method of selecting suitable frequency compensation for the control loop,a novel pole-zero tracking frequency compensation is proposed. Based on theoretical analysis, a DC-DC buck converter with high stability is designed with 0.5μm-CMOS technology. The simulated results reveal that the stability of the converter is independent of the load current and the input voltage. Moreover,the converter provides a full load transient response setting time of less than 5μs and overshoots and undershoots of less than 30mV.
文摘The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs,trading-off between the precision,speed,and size of the chip.In order to ensure the linearity of the DAC,a double Centro symmetric current matrix is designed by the Q2 random walk strategy.To achieve better dynamic performance,a latch is added in front of the current switch to change the input signal,such as its optimal cross-point and voltage level.For a 12bit resolution,the converter reaches an update rate of 300MHz.
