Due to not requiring channel state information （CSI） at both the transmitter and the receiver, noncoherent ultra-wideband （UWB） incurs a performance penalty of approximately 3 dB in the required signal to noise ra...Due to not requiring channel state information （CSI） at both the transmitter and the receiver, noncoherent ultra-wideband （UWB） incurs a performance penalty of approximately 3 dB in the required signal to noise ratio （SNR） compared to the coherent case. To overcome the gap, an effective differential encoding and decoding scheme for multiband UWB systems is proposed. The proposed scheme employs the parallel concatenation of two recursive differential unitary space-frequency encoders at the transmitter. At the receiver, two component decoders iteratively decode information bits by interchanging soft metric values between each other. To reduce the computation complexity, a decoding algorithm which only uses transition probability to calculate the log likelihood ratios （LLRs） for the decoded bits is given. Simulation results show that the proposed scheme can dramatically outperform the conventional differential and even coherent detection at high SNR with a few iterations.展开更多
On the basis of mutual compensation of mobility and threshold voltage temperature effects, a stable CMOS band-gap voltage reference circuit was designed and fabricated in CSMC-HJ 0.6 μm CMOS technology. Operating fro...On the basis of mutual compensation of mobility and threshold voltage temperature effects, a stable CMOS band-gap voltage reference circuit was designed and fabricated in CSMC-HJ 0.6 μm CMOS technology. Operating from 0 to 85 ℃ under a supply voltage ranging from 4.5 to 5.5 V, the voltage reference circuit offers an output reference voltage ranging from 1.122 to 1.176 V and a voltage variation less than ±3.70%. The chip size including bonding pads is only 0.4 mm×0.4 mm and the power dissipation falls inside the scope of 28.3 to 48.8 mW operating at a supply voltage of 4.5 to 5.5 V.展开更多
In this paper we describe a full-integrated circuit containing all building blocks of a completed PLL-based synthesizer except for low pass filter（LPF）. The frequency synthesizer is designed for a frequency hopping ...In this paper we describe a full-integrated circuit containing all building blocks of a completed PLL-based synthesizer except for low pass filter（LPF）. The frequency synthesizer is designed for a frequency hopping （FH） transceiver operating up to 1.5 GHz as a local oscillator. The architecture of Voltage Controlled Oscillator （VCO） is optimized to get better performance, and a phase noise of -111.85-dBc/Hz @ 1 MHz and a tuning range of 250 MHz are gained at a centre frequency of 1.35 GHz. A novel Dual-Modulus Prescaler（DMP） is designed to achieve a very low jitter and a lower power. The settling time of PLL is 80 μs while the reference frequency is 400 KHz.This monolithic frequency synthesizer is to integrate all main building blocks of PLL except for the low pass filter, with a maximum VCO output frequency of 1.5 GHz, and is fabricated with a 0.18 μm mixed signal CMOS process. Low power dissipation, low phase noise, large tuning range and fast settling time are gained in this design.展开更多
基金The Higher Education Technology Foundation of Huawei Technologies Co, Ltd (NoYJCB2005016WL)
文摘Due to not requiring channel state information （CSI） at both the transmitter and the receiver, noncoherent ultra-wideband （UWB） incurs a performance penalty of approximately 3 dB in the required signal to noise ratio （SNR） compared to the coherent case. To overcome the gap, an effective differential encoding and decoding scheme for multiband UWB systems is proposed. The proposed scheme employs the parallel concatenation of two recursive differential unitary space-frequency encoders at the transmitter. At the receiver, two component decoders iteratively decode information bits by interchanging soft metric values between each other. To reduce the computation complexity, a decoding algorithm which only uses transition probability to calculate the log likelihood ratios （LLRs） for the decoded bits is given. Simulation results show that the proposed scheme can dramatically outperform the conventional differential and even coherent detection at high SNR with a few iterations.
文摘On the basis of mutual compensation of mobility and threshold voltage temperature effects, a stable CMOS band-gap voltage reference circuit was designed and fabricated in CSMC-HJ 0.6 μm CMOS technology. Operating from 0 to 85 ℃ under a supply voltage ranging from 4.5 to 5.5 V, the voltage reference circuit offers an output reference voltage ranging from 1.122 to 1.176 V and a voltage variation less than ±3.70%. The chip size including bonding pads is only 0.4 mm×0.4 mm and the power dissipation falls inside the scope of 28.3 to 48.8 mW operating at a supply voltage of 4.5 to 5.5 V.
文摘In this paper we describe a full-integrated circuit containing all building blocks of a completed PLL-based synthesizer except for low pass filter（LPF）. The frequency synthesizer is designed for a frequency hopping （FH） transceiver operating up to 1.5 GHz as a local oscillator. The architecture of Voltage Controlled Oscillator （VCO） is optimized to get better performance, and a phase noise of -111.85-dBc/Hz @ 1 MHz and a tuning range of 250 MHz are gained at a centre frequency of 1.35 GHz. A novel Dual-Modulus Prescaler（DMP） is designed to achieve a very low jitter and a lower power. The settling time of PLL is 80 μs while the reference frequency is 400 KHz.This monolithic frequency synthesizer is to integrate all main building blocks of PLL except for the low pass filter, with a maximum VCO output frequency of 1.5 GHz, and is fabricated with a 0.18 μm mixed signal CMOS process. Low power dissipation, low phase noise, large tuning range and fast settling time are gained in this design.
