With the development of the modern information society, more and more multimedia information is available. So the technology of multimedia processing is becoming the important task for the irrelevant area of scientist...With the development of the modern information society, more and more multimedia information is available. So the technology of multimedia processing is becoming the important task for the irrelevant area of scientist. Among of the multimedia, the visual informarion is more attractive due to its direct, vivid characteristic, but at the same rime the huge amount of video data causes many challenges if the video storage, processing and transmission.展开更多
In this paper, a fast half-pixel motion estimation algorithm and its corresponding hardware architecture is presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented alg...In this paper, a fast half-pixel motion estimation algorithm and its corresponding hardware architecture is presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs only two steps to obtain all the interpolated pixels of an entire 8x8 block. The proposed architecture works in a parallel way and is simulated by Modelsirn 6.5 SE, synthesized to the Xilinx Virtex4 XC4VLX15 FPGA device. The implementation results show that this architecture can achieve 190 MHz and 10 clock cycles are reduced to complete the entire interpolation process when compared with typical half-pixel interpolation, which meets the requirements of real-time application for very high defination videos.展开更多
文摘With the development of the modern information society, more and more multimedia information is available. So the technology of multimedia processing is becoming the important task for the irrelevant area of scientist. Among of the multimedia, the visual informarion is more attractive due to its direct, vivid characteristic, but at the same rime the huge amount of video data causes many challenges if the video storage, processing and transmission.
文摘In this paper, a fast half-pixel motion estimation algorithm and its corresponding hardware architecture is presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs only two steps to obtain all the interpolated pixels of an entire 8x8 block. The proposed architecture works in a parallel way and is simulated by Modelsirn 6.5 SE, synthesized to the Xilinx Virtex4 XC4VLX15 FPGA device. The implementation results show that this architecture can achieve 190 MHz and 10 clock cycles are reduced to complete the entire interpolation process when compared with typical half-pixel interpolation, which meets the requirements of real-time application for very high defination videos.
