This paper describes a 3.0V, 10b,40Msample/s analog-to-digital converter （ADC） fabricated in a 0.25μm CMOS technology. Through the sharing an amplifier between two successive pipeline stages, the converter is reali...This paper describes a 3.0V, 10b,40Msample/s analog-to-digital converter （ADC） fabricated in a 0.25μm CMOS technology. Through the sharing an amplifier between two successive pipeline stages, the converter is realized using just four amplifiers with a separate sample-and-hold block. It employs two key techniques： a high bandwidth low-power gain-boosting telescopic amplifiers technique and a low power low offset dynamic comparators technique.The ADC achieves a 8.1 effective number of bits,a maximum differential nonlinearity of a 0.85 least significant bit（LSB）, and maximum integral nonlinearity of 2.2LSB for a 0.5MHz input at full sampling rate. It occupies 1.24mm^2 ,which also includes a bandgap and a voltage reference circuit and dissipates only 59mW.展开更多
A high-resolution,200kHz signal bandwidth,third-order single-loop single-bit ε△ modulator used in low-IF GSM receivers is presented. The modulator is implemented with fully differential switched capacitor circuits i...A high-resolution,200kHz signal bandwidth,third-order single-loop single-bit ε△ modulator used in low-IF GSM receivers is presented. The modulator is implemented with fully differential switched capacitor circuits in standard 0. 6μm 2P2M CMOS technology. The modulator uses two balanced reference voltages of ±1V,and is driven by a single 26MHz clock signal. The measurement results show that,with an oversampling ratio of 64, the modulator achieves an 80.6dB dynamic range,a 71.8dB peak SNDR,and a 73.9dB peak SNR in the signal bandwidth of 200kHz. The modulator dissipates 15mW static power from a single 5V supply.展开更多
A complementary metal-oxide-semiconductor transistor （CMOS） voltage-to-current（VTC）converter with high linearity for current-mode analog and digital integrated circuits is described. A high gain operational amplif...A complementary metal-oxide-semiconductor transistor （CMOS） voltage-to-current（VTC）converter with high linearity for current-mode analog and digital integrated circuits is described. A high gain operational amplifier （OPA） is utilized to form negative feedback. A proportional to absolute temperature （PTAT） current reference with transistors operated in a weak inversion is used as the bias circuit. The resistor and the OPA nonlinearity behavior are analyzed in detail. By optimizing parameters in OPA and adopting a small voltage coefficient polysilicon resistor as a linear device, a high linearity is achieved. The circuit is implemented in a standard 0. 6 μm CMOS technology. The low frequency gain of the OPA exceeds 90 dB. The test results indicate that the total harmonic distortion （THD）is 0. 000 2%. The common-mode input linearity range is 0 to 2. 6 V. Correspondingly, the output current range is 50 to 426μA. The sensitivity of the PTAT current reference to Vdd is approximately 0. 021 7. The chip consumes a power of less than 1.3 mW for a 5 V supply, and occupies an area of 0. 112 mm^2.展开更多
A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor shari...A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.展开更多
Batteries transfer management is one important aspect in electric vehicle(EV)network's intelligent operation management system.Batteries transfer is a special and much more complex VRP(Vehicle Routing Problem) whi...Batteries transfer management is one important aspect in electric vehicle(EV)network's intelligent operation management system.Batteries transfer is a special and much more complex VRP(Vehicle Routing Problem) which takes the multiple constraints such as dynamic multi-depots,time windows,simultaneous pickups and deliveries,distance minimization,etc.into account.We call it VRPEVB(VRP with EV Batteries).This paper,based on the intelligent management model of EV's battery power,puts forward a battery transfer algorithm for the EV network which considers the traffic congestion that changes dynamically and uses improved Ant Colony Optimization.By setting a reasonable tabv range,special update rules of the pheromone and path list memory functions,the algorithm can have a better convergence,and its feasibility is proved by the experiment in an EV's demonstration operation system.展开更多
This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in ...This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in a standard 0.18μm CMOS process with art active area of 0.5mm× 1.1mm.The EA modulator is driven by a single 19.2MHz clock signal and dissipates 5.88mW from 3V power supply. The experimental results show that,with an oversampling ratio of 48, the modulator achieves a 84.4dB dynamic range,73.8dB peak SNDR, and 80dB peak SNR in the signal bandwidth of 200kHz.展开更多
According to the anti-phase sine current superposition theorem, the orientation, the magnetic flux density, the angular speed and the rotational direction of the spatial universal rotating magnetic field (SURMF) can...According to the anti-phase sine current superposition theorem, the orientation, the magnetic flux density, the angular speed and the rotational direction of the spatial universal rotating magnetic field (SURMF) can be controlled within the tri-axial orthogonal square Helmholtz coils (TOSHC). Nevertheless, three coupling direction angles of the normal vector of the SURMF in the Descartes coordinate system cannot be separately controlled, thus the adjustment of the orientation of the SURMF is difficult and the flexibility of the robotic posture control is restricted. For the dimension reduction and the decoupling of control variables, the orthogonal transformation operation theorem of the SURMF is proposed based on two independent rotation angular variables, which employs azimuth and altitude angles as two variables of the three-phase sine current superposition formula derived by the orthogonal rotation inverse transformation. Then the unique control rules of the orientation and the rotational direction of the SURMF are generalized in each spatial quadrant, thus the scanning of the normal vector of the SURMF along the horizontal or vertical direction can be achieved through changing only one variable, which simplifies the control process of the orientation of the SURMF greatly. To validate its feasibility and maneuverability, experiments were conducted in the animal intestine utilizing the innovative dual hemisphere capsule robot (DHCR) with active and passive modes. It was demonstrated that the posture adjustment and the steering rolling locomotion of the DHCR can be realized through single variable control, thus the orthogonal transformation operation theorem makes the control of the orientation of the SURMF convenient and flexible significantly. This breakthrough will lay a foundation for the human-machine interaction control of the SURMF.展开更多
文摘This paper describes a 3.0V, 10b,40Msample/s analog-to-digital converter （ADC） fabricated in a 0.25μm CMOS technology. Through the sharing an amplifier between two successive pipeline stages, the converter is realized using just four amplifiers with a separate sample-and-hold block. It employs two key techniques： a high bandwidth low-power gain-boosting telescopic amplifiers technique and a low power low offset dynamic comparators technique.The ADC achieves a 8.1 effective number of bits,a maximum differential nonlinearity of a 0.85 least significant bit（LSB）, and maximum integral nonlinearity of 2.2LSB for a 0.5MHz input at full sampling rate. It occupies 1.24mm^2 ,which also includes a bandgap and a voltage reference circuit and dissipates only 59mW.
文摘A high-resolution,200kHz signal bandwidth,third-order single-loop single-bit ε△ modulator used in low-IF GSM receivers is presented. The modulator is implemented with fully differential switched capacitor circuits in standard 0. 6μm 2P2M CMOS technology. The modulator uses two balanced reference voltages of ±1V,and is driven by a single 26MHz clock signal. The measurement results show that,with an oversampling ratio of 64, the modulator achieves an 80.6dB dynamic range,a 71.8dB peak SNDR,and a 73.9dB peak SNR in the signal bandwidth of 200kHz. The modulator dissipates 15mW static power from a single 5V supply.
文摘A complementary metal-oxide-semiconductor transistor （CMOS） voltage-to-current（VTC）converter with high linearity for current-mode analog and digital integrated circuits is described. A high gain operational amplifier （OPA） is utilized to form negative feedback. A proportional to absolute temperature （PTAT） current reference with transistors operated in a weak inversion is used as the bias circuit. The resistor and the OPA nonlinearity behavior are analyzed in detail. By optimizing parameters in OPA and adopting a small voltage coefficient polysilicon resistor as a linear device, a high linearity is achieved. The circuit is implemented in a standard 0. 6 μm CMOS technology. The low frequency gain of the OPA exceeds 90 dB. The test results indicate that the total harmonic distortion （THD）is 0. 000 2%. The common-mode input linearity range is 0 to 2. 6 V. Correspondingly, the output current range is 50 to 426μA. The sensitivity of the PTAT current reference to Vdd is approximately 0. 021 7. The chip consumes a power of less than 1.3 mW for a 5 V supply, and occupies an area of 0. 112 mm^2.
基金supported by the Major National Science & Technology Program of China under Grant No.2012ZX03004004-002National High Technology Research and Development Program of China under Grant No. 2013AA014302
文摘A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.
基金supported by the 973 Program under Grant No.2011CB302506, 2012CB315802National Key Technology Research and Development Program of China under Grant No.2012BAH94F02+5 种基金The 863 Program under Grant No.2013AA102301NNSF of China under Grant No.61132001, 61170273Program for New Century Excel-lent Talents in University under Grant No. NCET-11-0592Project of New Generation Broad band Wireless Network under Grant No.2014ZX03006003The Technology Development and Experiment of Innovative Network Architecture(CNGI-12-03-007)The Open Fund Project of CAAC InformationTechnology Research Base(CAACITRB-201201)
文摘Batteries transfer management is one important aspect in electric vehicle(EV)network's intelligent operation management system.Batteries transfer is a special and much more complex VRP(Vehicle Routing Problem) which takes the multiple constraints such as dynamic multi-depots,time windows,simultaneous pickups and deliveries,distance minimization,etc.into account.We call it VRPEVB(VRP with EV Batteries).This paper,based on the intelligent management model of EV's battery power,puts forward a battery transfer algorithm for the EV network which considers the traffic congestion that changes dynamically and uses improved Ant Colony Optimization.By setting a reasonable tabv range,special update rules of the pheromone and path list memory functions,the algorithm can have a better convergence,and its feasibility is proved by the experiment in an EV's demonstration operation system.
文摘This paper introduces a high-revolution,200kHz signal bandwidth EA modulator for low-IF GSM receivers that adopts a 2-1 cascaded single-bit structure to achieve high linearity and stability. Our design is realized in a standard 0.18μm CMOS process with art active area of 0.5mm× 1.1mm.The EA modulator is driven by a single 19.2MHz clock signal and dissipates 5.88mW from 3V power supply. The experimental results show that,with an oversampling ratio of 48, the modulator achieves a 84.4dB dynamic range,73.8dB peak SNDR, and 80dB peak SNR in the signal bandwidth of 200kHz.
基金supported by the National Natural Science Foundation of China (Grant Nos. 51277018, 61175102, & 51475115)the Open Fund of the State Key Laboratory of Mechanical Transmissions (Grant No.SKLMT-KFKT-201509)
文摘According to the anti-phase sine current superposition theorem, the orientation, the magnetic flux density, the angular speed and the rotational direction of the spatial universal rotating magnetic field (SURMF) can be controlled within the tri-axial orthogonal square Helmholtz coils (TOSHC). Nevertheless, three coupling direction angles of the normal vector of the SURMF in the Descartes coordinate system cannot be separately controlled, thus the adjustment of the orientation of the SURMF is difficult and the flexibility of the robotic posture control is restricted. For the dimension reduction and the decoupling of control variables, the orthogonal transformation operation theorem of the SURMF is proposed based on two independent rotation angular variables, which employs azimuth and altitude angles as two variables of the three-phase sine current superposition formula derived by the orthogonal rotation inverse transformation. Then the unique control rules of the orientation and the rotational direction of the SURMF are generalized in each spatial quadrant, thus the scanning of the normal vector of the SURMF along the horizontal or vertical direction can be achieved through changing only one variable, which simplifies the control process of the orientation of the SURMF greatly. To validate its feasibility and maneuverability, experiments were conducted in the animal intestine utilizing the innovative dual hemisphere capsule robot (DHCR) with active and passive modes. It was demonstrated that the posture adjustment and the steering rolling locomotion of the DHCR can be realized through single variable control, thus the orthogonal transformation operation theorem makes the control of the orientation of the SURMF convenient and flexible significantly. This breakthrough will lay a foundation for the human-machine interaction control of the SURMF.
