A two-step gate-recess process combining high selective wet-etching and non-selective digital wet-etching techniques has been proposed for InAlAs/InGaAs InP-based high electron mobility transistors （HEMTs）. High etc...A two-step gate-recess process combining high selective wet-etching and non-selective digital wet-etching techniques has been proposed for InAlAs/InGaAs InP-based high electron mobility transistors （HEMTs）. High etching-selectivity ratio of InGaAs to InA1As material larger than 100 is achieved by using mixture solution of succinic acid and hydrogen peroxide （H202）. Selective wet-etching is validated in the gate-recess process of InA1As/InGaAs InP-based HEMTs, which proceeds and auto- matically stops at the InA1As barrier layer. The non-selective digital wet-etching process is developed using a separately controlled oxidation/de-oxidation technique, and during each digital etching cycle 1.2 nm InAIAs material is removed. The two-step gate-recess etching technique has been successfully incorporated into device fabrication. Digital wet-etching is repeated for two cycles with about 3 nm InAIAs barrier layer being etched off. InP-based HEMTs have demonstrated superior extrinsic trans- conductance and RF characteristics to devices fabricated during only the selective gate-recess etching process because of the smaller gate to channel distance.展开更多
基金Project supported by the National Natural Science Foundation of China （Nos. 61404115 and 61434006）, the Program for Innovative Research Team （in Science and Technology） in University of Henan Province, China （No. 18IRTSTHN016）, and the Development Fund for Outstanding Young Teachers in Zhengzhou University, China （No. 1521317004）
文摘A two-step gate-recess process combining high selective wet-etching and non-selective digital wet-etching techniques has been proposed for InAlAs/InGaAs InP-based high electron mobility transistors （HEMTs）. High etching-selectivity ratio of InGaAs to InA1As material larger than 100 is achieved by using mixture solution of succinic acid and hydrogen peroxide （H202）. Selective wet-etching is validated in the gate-recess process of InA1As/InGaAs InP-based HEMTs, which proceeds and auto- matically stops at the InA1As barrier layer. The non-selective digital wet-etching process is developed using a separately controlled oxidation/de-oxidation technique, and during each digital etching cycle 1.2 nm InAIAs material is removed. The two-step gate-recess etching technique has been successfully incorporated into device fabrication. Digital wet-etching is repeated for two cycles with about 3 nm InAIAs barrier layer being etched off. InP-based HEMTs have demonstrated superior extrinsic trans- conductance and RF characteristics to devices fabricated during only the selective gate-recess etching process because of the smaller gate to channel distance.
