The structures of the space switching and the wavelength switching optical cross connect (OXC) nodes which are based on the arrayed waveguide grating (AWG) multiplexer are analyzed.By the matrix transformation relatio...The structures of the space switching and the wavelength switching optical cross connect (OXC) nodes which are based on the arrayed waveguide grating (AWG) multiplexer are analyzed.By the matrix transformation relation between the input and output wavelengths of the AWG multiplexer, the wavelength transmission routings of the space switching and wavelength switching OXC nodes are determined.展开更多
Using CSMA/CD for EPON can eliminate the augmentations, such as multi-point control protocol and point-to-point emulation, added to the existing 802.3 architecture due to the incompatibility of PON to Ethernet. Both f...Using CSMA/CD for EPON can eliminate the augmentations, such as multi-point control protocol and point-to-point emulation, added to the existing 802.3 architecture due to the incompatibility of PON to Ethernet. Both full-duplex EPON system and half-duplex EPON system using CSMA/CD were proposed. In the full-duplex EPON, CSMA/CD is used as the upstream MAC protocol. In the half-duplex EPON system, both upstream and downstream traffic contend for the optical channel through CSMA/CD protocol. The upstream lightwave redirection and collision detection techniques were given. By the analysis and simulation, the throughput performance of the half-duplex EPON system is proven to be as well as that of the existing high speed half-duplex Ethernet LAN.展开更多
A low-power and high-speed 16:1 MUX IC designed for Optical fiber communication based on TSMC 0.25 μm CMOS technology is represented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at inp...A low-power and high-speed 16:1 MUX IC designed for Optical fiber communication based on TSMC 0.25 μm CMOS technology is represented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak-to-peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is （1.8） mm2.展开更多
Reasonable and effective buffer structures are proposed in core routers /nodes of optical burst switching.Based on the model of burst traffics and their contentions,the basic qualifications for the design of buffer st...Reasonable and effective buffer structures are proposed in core routers /nodes of optical burst switching.Based on the model of burst traffics and their contentions,the basic qualifications for the design of buffer structures are concluded.With these qualifications,buffer and switch integrated structures are proposed;and by conclusion and expansion,the classification rules of buffer structures are also proposed from different angles.The schemes to integrate structures are analyzed and simulated.展开更多
A monolithic clock-recovery circuit used in 622 Mb/s optical communication system is designed,which is based on the phase-locked loop theory,and uses bipolar transistor model.It overcomes the shortcoming of clock reco...A monolithic clock-recovery circuit used in 622 Mb/s optical communication system is designed,which is based on the phase-locked loop theory,and uses bipolar transistor model.It overcomes the shortcoming of clock recovery method based on filter,and implements monolithic clock-recovery IC.The designed circuits include phase detector,voltage-controlled oscillator and loop filter.Among them,the voltage-control oscillator is a modified two-stage ring oscillator,which provides quadrature clock signals and presents wide voltage-controlled range and high voltage-controlling sensitivity.展开更多
In this paper,the cause of bit-error is analyzed when data are decided in the optical receiver.A monolithic D-ff decision circuit is designed.It can work effectively at 622 Mb/s.Moreover,a decision method of parallel ...In this paper,the cause of bit-error is analyzed when data are decided in the optical receiver.A monolithic D-ff decision circuit is designed.It can work effectively at 622 Mb/s.Moreover,a decision method of parallel processing to improve the decision speed is presented,through which the parallel circuit can work up to 1 Gb/s using the same model.With the technique,higher-speed data can be decided by using lower speed device.展开更多
New generation passive optical network aims at providing more than 100 Gb/s capacity. Thanks to recent progress enabling a variety of optical transceivers up to 40 Gb/s, many evolution possibilities to 200G PONs （pas...New generation passive optical network aims at providing more than 100 Gb/s capacity. Thanks to recent progress enabling a variety of optical transceivers up to 40 Gb/s, many evolution possibilities to 200G PONs （passive optical network） could be investigated. This work proposes two directly deployable cases of evolution to 200G PON based on the combination of these improved optical transceivers and WDM （wavelength division multiplexing）. The physical layer of the optical network has been simulated with OptiSystem software to show the communication links performances behavior when considering key components parameters in order to achieve good network design for a given area. The complexity of the proposed architectures and financial cost comparisons are also discussed.展开更多
基金NationalKeyLabofBroadBandFiberTransmissionandCommunicatonSystemTechnology ElectronicUniversityofScienceandTechnology China
文摘The structures of the space switching and the wavelength switching optical cross connect (OXC) nodes which are based on the arrayed waveguide grating (AWG) multiplexer are analyzed.By the matrix transformation relation between the input and output wavelengths of the AWG multiplexer, the wavelength transmission routings of the space switching and wavelength switching OXC nodes are determined.
文摘Using CSMA/CD for EPON can eliminate the augmentations, such as multi-point control protocol and point-to-point emulation, added to the existing 802.3 architecture due to the incompatibility of PON to Ethernet. Both full-duplex EPON system and half-duplex EPON system using CSMA/CD were proposed. In the full-duplex EPON, CSMA/CD is used as the upstream MAC protocol. In the half-duplex EPON system, both upstream and downstream traffic contend for the optical channel through CSMA/CD protocol. The upstream lightwave redirection and collision detection techniques were given. By the analysis and simulation, the throughput performance of the half-duplex EPON system is proven to be as well as that of the existing high speed half-duplex Ethernet LAN.
文摘A low-power and high-speed 16:1 MUX IC designed for Optical fiber communication based on TSMC 0.25 μm CMOS technology is represented. A tree-type architecture was utilized. The output data bit rate is 2.5 Gb/s at input clock rate of 1.25 GHz. The simulation results show that the output signal has peak-to-peak amplitude of 400 mV, the power dissipation is less than 200 mW and the power dissipation of core circuit is less than 20 mW at the 2.5 Gb/s standard bit rate and supply voltage of 2.5 V. The chip area is （1.8） mm2.
文摘Reasonable and effective buffer structures are proposed in core routers /nodes of optical burst switching.Based on the model of burst traffics and their contentions,the basic qualifications for the design of buffer structures are concluded.With these qualifications,buffer and switch integrated structures are proposed;and by conclusion and expansion,the classification rules of buffer structures are also proposed from different angles.The schemes to integrate structures are analyzed and simulated.
文摘A monolithic clock-recovery circuit used in 622 Mb/s optical communication system is designed,which is based on the phase-locked loop theory,and uses bipolar transistor model.It overcomes the shortcoming of clock recovery method based on filter,and implements monolithic clock-recovery IC.The designed circuits include phase detector,voltage-controlled oscillator and loop filter.Among them,the voltage-control oscillator is a modified two-stage ring oscillator,which provides quadrature clock signals and presents wide voltage-controlled range and high voltage-controlling sensitivity.
文摘In this paper,the cause of bit-error is analyzed when data are decided in the optical receiver.A monolithic D-ff decision circuit is designed.It can work effectively at 622 Mb/s.Moreover,a decision method of parallel processing to improve the decision speed is presented,through which the parallel circuit can work up to 1 Gb/s using the same model.With the technique,higher-speed data can be decided by using lower speed device.
文摘New generation passive optical network aims at providing more than 100 Gb/s capacity. Thanks to recent progress enabling a variety of optical transceivers up to 40 Gb/s, many evolution possibilities to 200G PONs （passive optical network） could be investigated. This work proposes two directly deployable cases of evolution to 200G PON based on the combination of these improved optical transceivers and WDM （wavelength division multiplexing）. The physical layer of the optical network has been simulated with OptiSystem software to show the communication links performances behavior when considering key components parameters in order to achieve good network design for a given area. The complexity of the proposed architectures and financial cost comparisons are also discussed.
