In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC...In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.展开更多
An improved method of generating the self-balanced chaotic spread-spectrum code is presented. The chaotic-map pseudorandom sequence is used as the generated source. After a series of processing two-valued quantization...An improved method of generating the self-balanced chaotic spread-spectrum code is presented. The chaotic-map pseudorandom sequence is used as the generated source. After a series of processing two-valued quantization, inversion, all upside down, radix-S block upside down and shift combination, the proposed code is achieved. Theory analysis and simulation performance of the improved code are illustrated. And the results indicate that the suggested method gains a better performance than the traditional one by reasonable choices of the initial value and the S parameter in the im- proved method. Meanwhile the chaotic sequence＇ s characteristic of large addresses is inherited when the chaotic-map is used as the source. This advantage makes this improved code very suitable for the multiple access application in communication system.展开更多
文摘In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.
文摘An improved method of generating the self-balanced chaotic spread-spectrum code is presented. The chaotic-map pseudorandom sequence is used as the generated source. After a series of processing two-valued quantization, inversion, all upside down, radix-S block upside down and shift combination, the proposed code is achieved. Theory analysis and simulation performance of the improved code are illustrated. And the results indicate that the suggested method gains a better performance than the traditional one by reasonable choices of the initial value and the S parameter in the im- proved method. Meanwhile the chaotic sequence＇ s characteristic of large addresses is inherited when the chaotic-map is used as the source. This advantage makes this improved code very suitable for the multiple access application in communication system.
