A novel flash memory cell with stacked structure （Si substrate/SiGe quantum dots/tunneling oxide/polySi floating gate） is proposed and demonstrated to achieve enhanced F-N tunneling for both programming and erasing....A novel flash memory cell with stacked structure （Si substrate/SiGe quantum dots/tunneling oxide/polySi floating gate） is proposed and demonstrated to achieve enhanced F-N tunneling for both programming and erasing. Simulation results indicate the new structure provides high speed and reliability. Experimental results show that the operation voltage can be as much as 4V less than that of conventional full F-N tunneling NAND memory cells. Memory cells with the proposed structure can achieve higher speed, lower voltage, and higher reliability.展开更多
Proposed herein is a novel non planar cell structure for flash memory which has been fabricated to achieve high programming speed with low operating voltage.This memory cell preserves a simple stacked gate structure ...Proposed herein is a novel non planar cell structure for flash memory which has been fabricated to achieve high programming speed with low operating voltage.This memory cell preserves a simple stacked gate structure which only requires an additional masking step to form the novel structure in the channel.For the cell of the 1 2μm gate length,the programming speed of 43μs under the measuring condition of V g=15V, V d=5V,and the erasing time of 24ms under V g=-5V, V s=8V are obtained.The programming speed is faster than that of the conventional planar cell structure.This superior programming speed makes it suitable for high speed application.展开更多
Step channel direct injection(SCDI)flash memory device which had been developed changes the hot carrier injection method by making a shallow step in the middle of channel .Therefore high speed for programming,hig...Step channel direct injection(SCDI)flash memory device which had been developed changes the hot carrier injection method by making a shallow step in the middle of channel .Therefore high speed for programming,high efficiency for injection,and lower working voltage are obtained.Simulation and analysis for the proposed SCDI structure device are done and an optimization scheme to improve the utmost performance of SCDI device is given...展开更多
Step channel direct injection(SCDI) flash memory device is successfully achieved by 1 2μm CMOS technology,moreover good performance is obtained.At the bias condition of V g=6V, V d=5V,the programming speed ...Step channel direct injection(SCDI) flash memory device is successfully achieved by 1 2μm CMOS technology,moreover good performance is obtained.At the bias condition of V g=6V, V d=5V,the programming speed of SCDI device is 42μs.Under the condition of V g=-8V, V s=8V,the erasing speed is 24ms.Compared with the same size of conventional flash memory device whose corresponding parameters are 500μs and 24ms,respectively,the performance of SCDI device is remarkably improved.During manufacturing of SCDI device,the key technologies are to make the shallow step with appropriate depth and angle,along with eliminating the etch damage during the process of Si 3N 4 spacer.展开更多
With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and...With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.展开更多
随着电路设计向着小型化的方向发展,PSD(Programmable System Devices)器件在各种场合的应用越来越多,已经有很多成型的产品出现;而且随着器件的更新换代,新的PSD器件也不断地涌现,可以满足绝大多数客户的应用需求。本文以最近生产的一...随着电路设计向着小型化的方向发展,PSD(Programmable System Devices)器件在各种场合的应用越来越多,已经有很多成型的产品出现;而且随着器件的更新换代,新的PSD器件也不断地涌现,可以满足绝大多数客户的应用需求。本文以最近生产的一种在系统可编程(ISP)器件PSD913F2为例,详细说明如何对它进行开发使用。展开更多
文摘A novel flash memory cell with stacked structure （Si substrate/SiGe quantum dots/tunneling oxide/polySi floating gate） is proposed and demonstrated to achieve enhanced F-N tunneling for both programming and erasing. Simulation results indicate the new structure provides high speed and reliability. Experimental results show that the operation voltage can be as much as 4V less than that of conventional full F-N tunneling NAND memory cells. Memory cells with the proposed structure can achieve higher speed, lower voltage, and higher reliability.
文摘Proposed herein is a novel non planar cell structure for flash memory which has been fabricated to achieve high programming speed with low operating voltage.This memory cell preserves a simple stacked gate structure which only requires an additional masking step to form the novel structure in the channel.For the cell of the 1 2μm gate length,the programming speed of 43μs under the measuring condition of V g=15V, V d=5V,and the erasing time of 24ms under V g=-5V, V s=8V are obtained.The programming speed is faster than that of the conventional planar cell structure.This superior programming speed makes it suitable for high speed application.
文摘Step channel direct injection(SCDI)flash memory device which had been developed changes the hot carrier injection method by making a shallow step in the middle of channel .Therefore high speed for programming,high efficiency for injection,and lower working voltage are obtained.Simulation and analysis for the proposed SCDI structure device are done and an optimization scheme to improve the utmost performance of SCDI device is given...
文摘Step channel direct injection(SCDI) flash memory device is successfully achieved by 1 2μm CMOS technology,moreover good performance is obtained.At the bias condition of V g=6V, V d=5V,the programming speed of SCDI device is 42μs.Under the condition of V g=-8V, V s=8V,the erasing speed is 24ms.Compared with the same size of conventional flash memory device whose corresponding parameters are 500μs and 24ms,respectively,the performance of SCDI device is remarkably improved.During manufacturing of SCDI device,the key technologies are to make the shallow step with appropriate depth and angle,along with eliminating the etch damage during the process of Si 3N 4 spacer.
基金supported in part by the NSF of China (61471131, 61771149, 61501126)NSF of Guangdong Province 2016A030310337+1 种基金the open research fund of National Mobile Communications Research Laboratory, Southeast University (No. 2018D02)the Guangdong Province Universities and Colleges Pearl River Scholar Funded Scheme (2017-ZJ022)
文摘With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.
文摘随着电路设计向着小型化的方向发展,PSD(Programmable System Devices)器件在各种场合的应用越来越多,已经有很多成型的产品出现;而且随着器件的更新换代,新的PSD器件也不断地涌现,可以满足绝大多数客户的应用需求。本文以最近生产的一种在系统可编程(ISP)器件PSD913F2为例,详细说明如何对它进行开发使用。
