数字逻辑课程设计的教学探索

课程设计是一门研究型课程,是工科专业课程教学中的一个重要环节,具有很强的综合性和实践性。如何利用这一课程的特点,组织实施好课程设计教学,已成为教学改革中值得深究的问题。本文针对数字逻辑课程设计教学中存在的问题,结合近年来笔者实践教学和探索经历中的体会,阐述了一些行之有效的教学方法并提出了一些设想。

逻:用于表示以自然天险为边境的界碑--《大唐西域记》汉译地名研究札记

《大唐西域记》汉译地名出现的逻字,一方面是西域语的音译,具有标音作用;另一方面,又包含意译因素,表示名称所指对象,处于自然天险的边缘,以高山大川等作为边界。这类名称涉及作为边界的西域邦国、城邑、山水,集中分布在南亚次大陆北端,以古代北印度、覩货逻故地居多。作为邦国、城邑、山水、边境的天险有葱岭、印度河、喜马拉雅山等,都是高山巨川。书中的逻字暗含边缘、遮拦两种意义,在词语义项演变链条中处于重要环节。

FAULT DETECTION FOR MULTIPLE-VALUED LOGIC CIRCUITS WITH FANOUT-FREE

The single fault and multiple fault detections for multiple-valued logic circuits are studied in this paper. Firstly, it is shown that the cardinality of optimal single fault test set for fanout-free m-valued circuits with n primary inputs is not more than n + 1, for linear tree circuits is two, and for multiplication modulo circuits is two if n is an odd number or if n is an even number and m ＞ 3, where the optimal test set of a circuit has minimal number of test vectors. Secondly,it is indicated that the cardinality of optimal multiple fault test set for linear tree circuits with n primary inputs is 1 + [n/(m - 1)], for multiplication modulo circuits is n+ 1, for fanout-free circuits that consist of 2-input linear tree circuits and 2-input multiplication modulo circuits is not greater than n+ 1, where [x] denotes the smallest integer greater than or equal to x. Finally,the single fault location approaches of linear tree circuits and multiplication modulo circuits are presented, and all faults in the two types of circuits can be located by using a test set with n + 1 vectors.

Quasi-Static Energy Recovery Logic with Single Power-Clock Supply

This paper presents a new quasi-static single-phase energy recovery logic （QSSERL）, which unlike any other existing adiabatic logic family,uses a single sinusoidal supply-clock without additional timing control volta- ges. This not only ensures lower energy dissipation, but also simplifies the clock design, which would be otherwise more complicated due to the signal synchronization requirement. It is demonstrated that QSSERL circuits operate as fast as conventional two-phase energy recovery logic counterparts. Simulation with an 8bit logarithmic look- ahead adder （LLA） using static CMOS,clocked CMOS adiabatic logic （CAL,an existing typical single-phase ener- gy recovery logic）,and QSSERL,under 128 randomly generated input vectors,shows that the power consumption of the QSSERL adder is only 45% of that of the conventional static CMOS counterpart at 10MHz, and the QS- SERL adder achieves better energy efficiency than CAL when the input frequency finput is larger than 2MHz.

Adding Pseudo-Random Test Sequence Generator in the Test Simulator for DFT Approach

This paper presents modified version of a realistic test tool suitable to Design For Testability （DFT） and Built-ln Self Test （BIST） environments. A comprehensive tool is developed in the form of a test simulator. The simulator is capable of providing a required goal of test for the Circuit Under Test （CUT）. The simulator uses the approach of fault diagnostics with fault grading procedures to provide the optimum tests. The current version of the simulator embeds features of exhaustive and pseudo-random test generation schemes along with the search solutions of cost effective test goals. The simulator provides facilities of realizing all possible pseudo-random sequence generators with all possible combinations of seeds. The tool is developed on a common Personal Computer （PC） platform and hence no special software is required. Thereby, it is a low cost tool hence economical. The tool is very much suitable for determining realistic test sequences for a targeted goal of testing for any CUT. The developed tool incorporates flexible Graphical User Interface （GUI） procedures and can be operated without any special programming skill. The tool is debugged and tested with the results of many bench mark circuits. Further, this developed tool can be utilized for educational purposes for many courses such as fault-tolerant computing, fault diagnosis, digital electronics, and safe-reliable-testable digital logic designs.

DESIGN OF MULTI-SERVICE SDH NETWORKS: FORMULATION AND HEURISTICS

Multi-service SDH networks support both packet- and circuit-switched traffic. Optimal design of such a network means to guarantee the circuit connections and configure a logical packet-switched topology with lowest congestion. This letter first formulates the problem as a mixed integer linear programming, which achieves optimal solution but has high computation. Then a heuristic algorithm is proposed to yield near-optimal solution efficiently. Performance of the algorithm is verified by an example.

THE DESIGN OF VMEBUS BRIDGE CONTROLLER WITH SHARC BUS

Targeting at the high expense and inflexibility to realize VMEbus bridge controller by professional Integrated Circuit (IC), this paper presents a scheme of adopting CPLD/FPGA (Complicated Programmable Logic Device/Field Programmable Gate Array) to design bridge controller between VMEbus and local bus. SHARC DSP (Digital Signal Processor) bus is an example. It has functions of nearly entire master/slave interface of VMEbus, and can act as DMA (Direct Memory Access) controller and perform block transfer in DMA or master processor initiative way without length limit. External circuit of the design is very simple. In comparison with special ICs, it has high performance to price ratio and can be easily applied to local buses of other processors with quite a little modification.

Efficient Modeling of Photovoltaic Systems Using CMEX S-Function under MATLAB-Simulink Environment

This paper discusses an implementation based on CMEX S-functions to model and to check implementation feasibility of two most commonly used Maximum Power Point Tracking （MPPT） algorithms, namely Hill Climbing/Perturb ＆ Observe （P＆O） and Incremental Conductance. This study can also be generalized to encompass the whole digital techniques family, including artificial intelligence like Neural Network and Fuzzy Logic Control.

Digital Ecologies as Tractarian Systems

This paper explores Wittgenstein＇s early work as it relates to emerging philosophical problems in ecological modeling. Here I use his thought to structure a logical framework from which to discuss ecological simulation models in a way that captures how these dynamic representations describe a world from which we can draw logical inferences about real-world ecological processes. I argue that Wittgenstein＇s Tractatus Logico-Philosophicus provides a way of reading problems that arise in using simulation as a way to make inferences about the world. Conversely, ecological simulation provides an illustration of a Tractarian system, because the digital world it creates completely describes and is defined by the programing language. This reading is a novel, but productive, way that notes that the language used in modeling requires a hermeneutical approach to make inferences about modeling/real-world relationships.

The most robust design for digital logics of multiple variables based on neurons with complex-valued weights

Neurons with complex-valued weights have stronger capability because of their multi-valued threshold logic. Neurons with such features may be suitable for solution of different kinds of problems including associative memory,image recognition and digital logical mapping. In this paper,robustness or tolerance is introduced and newly defined for this kind of neuron ac-cording to both their mathematical model and the perceptron neuron's definition of robustness. Also,the most robust design for basic digital logics of multiple variables is proposed based on these robust neurons. Our proof procedure shows that,in robust design each weight only takes the value of i or -i,while the value of threshold is with respect to the number of variables. The results demonstrate the validity and simplicity of using robust neurons for realizing arbitrary digital logical functions.