This paper presents an optimized SRAM that is repairable and dissipates less power. To improve the yield of SRAMs per wafer,redundancy logic and an E-FUSE box are added to the SRAM and an SR SRAM is set up. In order t...This paper presents an optimized SRAM that is repairable and dissipates less power. To improve the yield of SRAMs per wafer,redundancy logic and an E-FUSE box are added to the SRAM and an SR SRAM is set up. In order to reduce power dissipation,power on/off states and isolation logic are introduced into the SR SRAM and an LPSR SRAM is constructed. The optimized LPSR SRAM64K × 32 is used in SoC and the testing method of the LPSR SRAM64K × 32 is also discussed. The SoC design is successfully implemented in the Chartered 90nm CMOS process. The SoC chip occupies 5. 6mm× 5. 6ram of die area and the power dissipation is 1997mW. The test results indicate that LPSR SRAM64K ×32 obtains 17. 301% power savings and the yield of the LPSR SRAM64K × 32s per wafer is improved by 13. 255%.展开更多
Power control is of paramount importance in combating the near-far problem and co-channel interference in a CDMA cellular system. Due to fast fading and ambient interference in a wireless channel, conventional fixed-s...Power control is of paramount importance in combating the near-far problem and co-channel interference in a CDMA cellular system. Due to fast fading and ambient interference in a wireless channel, conventional fixed-step power control schemes have difficulty in compensating for the fast fading channel dynamically and in a timely manner. To acquire flexible power regulation in order to maintain required transmission capacity under the given transmission quality requirement, we propose a hybrid power control scheme which makes full use of the simple fuzzy inference rule refined by an operator in the fuzzy control and prediction property from related previous results in Generalized Prediction Control (GPC). In implementation of this strategy, we classify the fading zone into three levels according to the signal-to-noise-rate (SNR) requirement. In each level the power compensation amount varies with fading gradient and the compensation scheme varies as well. The digital results show that adoption of the fuzzy-GPC power regulation scheme has acquired a reasonable performance improvement when compared with fixed-step and fuzzy schemes. According to theoretic analysis and simulation results, we can conclude that under a variational transmission environment, a flexible power regulation scheme such as fuzzy-GPC is easy to adapt to the environment and thus overcomes the near-far effect and multi-access interference effectively.展开更多
Power analysis is a non-invaslve attack against cryptographic hardware, which effectively exploits runtime power consumption characteristics of circuits. This paper proposes a new power model which combines Hamming Di...Power analysis is a non-invaslve attack against cryptographic hardware, which effectively exploits runtime power consumption characteristics of circuits. This paper proposes a new power model which combines Hamming Distance model and the model based on the template value of power consumption in combinational logic circuit. The new model can describe the power consumption characteristics of sequential logic circuits and those of combinational logic as well. The new model can be used to improve the existing power analysis methods and detect the information leakage of power consumption. Experimental results show that, compared to CPA（Correlation Power Analysis） method, our proposed attack which adopt the combinational model is more efficient in terms of the number of required power traces.展开更多
We propose a single-poly MTP （multi-time programmable） cell consisting of one capacitor and two transistors based on MagnaChip＇s BCD process. The area of a unit cell is 37.743 75μm^2. The proposed single-poly MTP ...We propose a single-poly MTP （multi-time programmable） cell consisting of one capacitor and two transistors based on MagnaChip＇s BCD process. The area of a unit cell is 37.743 75μm^2. The proposed single-poly MTP cell is erased and programmed by the FN tunnelling scheme. We design a 256 bit MTP memory for PMICs （power management ICs） using the proposed single-poly MTP cells. For small-area designs, we propose a selection circuit between V10V and VSV, and a WL （word-line） driver by simplifying its logic circuit. We reduce the total layout area by using pumped internal node voltages from a seven-stage cross-coupled charge pump for V10V （=10 V） and V5V （=5 V） without any additional charge pumps. The layout size of the designed 256 bit MTP memory is 618.250 μm × 437.425μm.展开更多
文摘This paper presents an optimized SRAM that is repairable and dissipates less power. To improve the yield of SRAMs per wafer,redundancy logic and an E-FUSE box are added to the SRAM and an SR SRAM is set up. In order to reduce power dissipation,power on/off states and isolation logic are introduced into the SR SRAM and an LPSR SRAM is constructed. The optimized LPSR SRAM64K × 32 is used in SoC and the testing method of the LPSR SRAM64K × 32 is also discussed. The SoC design is successfully implemented in the Chartered 90nm CMOS process. The SoC chip occupies 5. 6mm× 5. 6ram of die area and the power dissipation is 1997mW. The test results indicate that LPSR SRAM64K ×32 obtains 17. 301% power savings and the yield of the LPSR SRAM64K × 32s per wafer is improved by 13. 255%.
文摘Power control is of paramount importance in combating the near-far problem and co-channel interference in a CDMA cellular system. Due to fast fading and ambient interference in a wireless channel, conventional fixed-step power control schemes have difficulty in compensating for the fast fading channel dynamically and in a timely manner. To acquire flexible power regulation in order to maintain required transmission capacity under the given transmission quality requirement, we propose a hybrid power control scheme which makes full use of the simple fuzzy inference rule refined by an operator in the fuzzy control and prediction property from related previous results in Generalized Prediction Control (GPC). In implementation of this strategy, we classify the fading zone into three levels according to the signal-to-noise-rate (SNR) requirement. In each level the power compensation amount varies with fading gradient and the compensation scheme varies as well. The digital results show that adoption of the fuzzy-GPC power regulation scheme has acquired a reasonable performance improvement when compared with fixed-step and fuzzy schemes. According to theoretic analysis and simulation results, we can conclude that under a variational transmission environment, a flexible power regulation scheme such as fuzzy-GPC is easy to adapt to the environment and thus overcomes the near-far effect and multi-access interference effectively.
基金supported by Major State Basic Research Development Program(No. 2013CB338004)National Natural Science Foundation of China(No.61402286, 61202372,61202371,61309021)National Science and Technology Major Project of the Ministry of Science and Technology of China (No.2014ZX01032401-001)
文摘Power analysis is a non-invaslve attack against cryptographic hardware, which effectively exploits runtime power consumption characteristics of circuits. This paper proposes a new power model which combines Hamming Distance model and the model based on the template value of power consumption in combinational logic circuit. The new model can describe the power consumption characteristics of sequential logic circuits and those of combinational logic as well. The new model can be used to improve the existing power analysis methods and detect the information leakage of power consumption. Experimental results show that, compared to CPA（Correlation Power Analysis） method, our proposed attack which adopt the combinational model is more efficient in terms of the number of required power traces.
基金Project supported by the Second Stage of Brain Korea 21 Projectssupported by Industrial Strategic Technology Development Program funded by the Ministry of Knowledge Economy (MKE,Korea)(10039239,"Development of Power Management System SoC Supporting Multi-Battery-Cells and Multi-Energy-Sources for Smart Phones and Smart Devices")
文摘We propose a single-poly MTP （multi-time programmable） cell consisting of one capacitor and two transistors based on MagnaChip＇s BCD process. The area of a unit cell is 37.743 75μm^2. The proposed single-poly MTP cell is erased and programmed by the FN tunnelling scheme. We design a 256 bit MTP memory for PMICs （power management ICs） using the proposed single-poly MTP cells. For small-area designs, we propose a selection circuit between V10V and VSV, and a WL （word-line） driver by simplifying its logic circuit. We reduce the total layout area by using pumped internal node voltages from a seven-stage cross-coupled charge pump for V10V （=10 V） and V5V （=5 V） without any additional charge pumps. The layout size of the designed 256 bit MTP memory is 618.250 μm × 437.425μm.
