As feature sizes shrink,low energy consumption,high reliability and high performance become key objectives of network-on-chip(NoC) design.In this paper,an integrated approach is presented to map IP cores onto NoC arch...As feature sizes shrink,low energy consumption,high reliability and high performance become key objectives of network-on-chip(NoC) design.In this paper,an integrated approach is presented to map IP cores onto NoC architecture and assign voltage levels for each link,such that the communication energy is minimized under constraints of bandwidth and reliability.The design space is explored using tabu search.In order to select optimal voltage level for the links,an energy-efficiency driven heuristic algorithm is proposed to perform energy/reliability trade-off by exploiting communication slack.Experimental results show that the ordinary energy optimization techniques ignoring the influence of voltage on fault rates could lead to drastically decreased communication reliability of NoCs,and the proposed approach can produce reliable and energy-efficient implementations.展开更多
The function-layer model and working model of collaborative remote fault diagnosis system （FDS）, which includes three layers： task layer, collaboration layer and diagnosing layer, are proposed. The running mechanis...The function-layer model and working model of collaborative remote fault diagnosis system （FDS）, which includes three layers： task layer, collaboration layer and diagnosing layer, are proposed. The running mechanism of the system is discussed. A collaborative FDS may consist of several subsystems running at different places and the subsystem consists of several fimction modules. A structure centered on data-bus is adopted in subsystem. All the function modules in subsystem are encapsulated into software intelligent chips （SICs） and SIC can but connect with data-bus. So, it is feasible to reuse these diagnosis fimction modules and the structure of subsystem in different diagnosis applications. With the reconfigurable SICs, several different function modules can reconstruct quickly some different diagnosis subsystems in different combinations, and some subsystems can also reconfigure a specified collaborative FDS.展开更多
A Y-band frequency doubler is analyzed and designed with GaAs planar Schottky diode, which is flip-chip solded into a 50 μm thick quartz substrate. Diode embedding impedance is found by full- wave analysis with lumpe...A Y-band frequency doubler is analyzed and designed with GaAs planar Schottky diode, which is flip-chip solded into a 50 μm thick quartz substrate. Diode embedding impedance is found by full- wave analysis with lumped port to model the nonlinear junction for impedance matching without the need of diode equivalent circuit model. All the matching circuit is designed ＂on-chip＂ and the mul- tiplier is self-biasing. To the doubler, a conversion efficiency of 6.1% and output power of 5.4mW are measured at 214GHz with input power of 88mW, and the typical measured efficiency is 4.5% in 200 - 225 GHz.展开更多
基金Supported by the Natural Science Foundation of China(No.61003032,61100118)Artificial Intelligence Key Laboratory of Sichuan Province of China(No.2010RY010,2011RYJ05)
文摘As feature sizes shrink,low energy consumption,high reliability and high performance become key objectives of network-on-chip(NoC) design.In this paper,an integrated approach is presented to map IP cores onto NoC architecture and assign voltage levels for each link,such that the communication energy is minimized under constraints of bandwidth and reliability.The design space is explored using tabu search.In order to select optimal voltage level for the links,an energy-efficiency driven heuristic algorithm is proposed to perform energy/reliability trade-off by exploiting communication slack.Experimental results show that the ordinary energy optimization techniques ignoring the influence of voltage on fault rates could lead to drastically decreased communication reliability of NoCs,and the proposed approach can produce reliable and energy-efficient implementations.
文摘The function-layer model and working model of collaborative remote fault diagnosis system （FDS）, which includes three layers： task layer, collaboration layer and diagnosing layer, are proposed. The running mechanism of the system is discussed. A collaborative FDS may consist of several subsystems running at different places and the subsystem consists of several fimction modules. A structure centered on data-bus is adopted in subsystem. All the function modules in subsystem are encapsulated into software intelligent chips （SICs） and SIC can but connect with data-bus. So, it is feasible to reuse these diagnosis fimction modules and the structure of subsystem in different diagnosis applications. With the reconfigurable SICs, several different function modules can reconstruct quickly some different diagnosis subsystems in different combinations, and some subsystems can also reconfigure a specified collaborative FDS.
基金Supported by the 12th Five-year Defense Pre-research Fund of China(No.51308030509)
文摘A Y-band frequency doubler is analyzed and designed with GaAs planar Schottky diode, which is flip-chip solded into a 50 μm thick quartz substrate. Diode embedding impedance is found by full- wave analysis with lumped port to model the nonlinear junction for impedance matching without the need of diode equivalent circuit model. All the matching circuit is designed ＂on-chip＂ and the mul- tiplier is self-biasing. To the doubler, a conversion efficiency of 6.1% and output power of 5.4mW are measured at 214GHz with input power of 88mW, and the typical measured efficiency is 4.5% in 200 - 225 GHz.
