QCr0.8 was electron-beam welded to TC4 and the effect of the intermetallic layer （IMC-layer） on the mechanical properties of the joint was investigated. The IMC-layers are joint weaknesses at the Cu fusion line in c...QCr0.8 was electron-beam welded to TC4 and the effect of the intermetallic layer （IMC-layer） on the mechanical properties of the joint was investigated. The IMC-layers are joint weaknesses at the Cu fusion line in centered welding and at the Ti fusion line when the beam is deviated towards Cu. A new method referred to as electron-beam superposition welding was presented, and the optimal welding sequence was considered. The IMC-layer produced by centered welding was fragmented and remelted during Cu-side non-centered welding, giving a finely structured compound layer and improved mechanical properties of the joint. The tensile strength of joint is 276.0 MPa, 76.7% that of the base metal.展开更多
By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length a...By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. The key technologies adopted to restrain SCE and to improve drive ability include a 1.7nm N/O stack gate dielectric, non-CMP planarization technology, a T-type refractory W/TiN metal stack gate electrode, and a novel super steep retrograde channel doping using heavy ion implantation and a double sidewall scheme. Using these optimized key technologies, high performance 95nm metal gate CMOS devices with excellent SCE and good driving ability are fabricated. Under power supply voltages of VDS ± 1.5V and VGS± 1.8V,drive currents of 679μA/μm for nMOS and - 327μA/μm for pMOS are obtained. A subthreshold slope of 84.46mV/dec, DIBL of 34.76mV/V, and Vth of 0.26V for nMOS, and a subthreshold slope of 107.4mV/dec,DIBL of 54.46mV/V, and Vth of 0.27V for pMOS are achieved. These results show that the combined technology has indeed thoroughly eliminated the boron penetration phenomenon and polysilicon depletion effect ,effectively reduced gate tunneling leakage, and improved device reliability.展开更多
基金Project (2010CB731704) supported by the National Basic Research Program of China
文摘QCr0.8 was electron-beam welded to TC4 and the effect of the intermetallic layer （IMC-layer） on the mechanical properties of the joint was investigated. The IMC-layers are joint weaknesses at the Cu fusion line in centered welding and at the Ti fusion line when the beam is deviated towards Cu. A new method referred to as electron-beam superposition welding was presented, and the optimal welding sequence was considered. The IMC-layer produced by centered welding was fragmented and remelted during Cu-side non-centered welding, giving a finely structured compound layer and improved mechanical properties of the joint. The tensile strength of joint is 276.0 MPa, 76.7% that of the base metal.
文摘By complementing the equivalent oxide thickness （EOT） of a 1.7nm nitride/oxynitride （N/O） stack gate dielectric （EOT- 1.7nm） with a W/TiN metal gate electrode,metal gate CMOS devices with sub-100nm gate length are fabricated in China for the first time. The key technologies adopted to restrain SCE and to improve drive ability include a 1.7nm N/O stack gate dielectric, non-CMP planarization technology, a T-type refractory W/TiN metal stack gate electrode, and a novel super steep retrograde channel doping using heavy ion implantation and a double sidewall scheme. Using these optimized key technologies, high performance 95nm metal gate CMOS devices with excellent SCE and good driving ability are fabricated. Under power supply voltages of VDS ± 1.5V and VGS± 1.8V,drive currents of 679μA/μm for nMOS and - 327μA/μm for pMOS are obtained. A subthreshold slope of 84.46mV/dec, DIBL of 34.76mV/V, and Vth of 0.26V for nMOS, and a subthreshold slope of 107.4mV/dec,DIBL of 54.46mV/V, and Vth of 0.27V for pMOS are achieved. These results show that the combined technology has indeed thoroughly eliminated the boron penetration phenomenon and polysilicon depletion effect ,effectively reduced gate tunneling leakage, and improved device reliability.
