In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for...In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop （PLL） in frequency control and an automatic gain control （AGC） method in amplitude control. A digital processing circuit with a field programmable gate array （FPGA） is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.展开更多
A new method for the control of the speed of an ultrasonic motor and its implementation are proposed. The method is merely used by detecting the time when motor′s monitor signal reaches a non zero reference valu...A new method for the control of the speed of an ultrasonic motor and its implementation are proposed. The method is merely used by detecting the time when motor′s monitor signal reaches a non zero reference value than a zero one, the direction, in which the driving frequency of the motor should be shifted, can be promptly calculated. With the aid of a CPU and the phase locked frequency doubling technique, the motor can be steadily driven in a wide range of frequency and the optimum frequency can be captured rapidly and precisely. Experiment shows that the above method is available.展开更多
A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short...A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.展开更多
A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator ...A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.展开更多
In this paper the method of multiple scales is used to study the nonlinear dynamics of the ice soil platform system. Results show that the system exhibits multiple kinds of combination re...In this paper the method of multiple scales is used to study the nonlinear dynamics of the ice soil platform system. Results show that the system exhibits multiple kinds of combination resonances and that its natural frequencies accord with the testing results of the model platform. Under the condition of primary resonance,we discussed the nonlinear dynamic characteristics of self excited, locking,forced vibrations. They conform to the on site observation. This paper explains the ice induced vibration mechanism and thus establishes an appropriate mechanical model for the nonlinear analysis of the offshore platform systems.展开更多
Several key techniques for a PLL-type frequency synthesizer for WLAN receivers are studied. Its structure is analyzed and the main parameters are proposed. A monolithic LC-tuned voltage controlled oscillator （LCVCO）...Several key techniques for a PLL-type frequency synthesizer for WLAN receivers are studied. Its structure is analyzed and the main parameters are proposed. A monolithic LC-tuned voltage controlled oscillator （LCVCO） with low phase noise is fabricated with TSMC 0.18μm RF （radio frequency） CMOS technology. The measured phase noise is - ll7dBc/Hz at 4MHz off the center frequency of 4. 189GHz. A down-scaling circuit with low power dissipation was fabricated in a TSMC 0.18μm mixed-signal CMOS process. The measured results show that the IC can work well under a 1.8V power supply. Its total power dissipation is only 13mW.展开更多
An improved on-chip CMOS astable multivibrator is proposed, which overcomes the shortcomings of the traditional one that the signal duty-cycle is depending on model parameters, and generates stable clock signal with d...An improved on-chip CMOS astable multivibrator is proposed, which overcomes the shortcomings of the traditional one that the signal duty-cycle is depending on model parameters, and generates stable clock signal with duty-cycle equaling 50%. The latch-up effect has been prevented on the improved circuit. It is extremely important that all the excellent performances of the improved astable multivibrator have been achieved with a dynamic power consumption equaling its predecessor one. The advantage of the structure has been verified by SPICE simulation.展开更多
Oscillator IC technique is developed by combining injecting synchronization technique with a ring VCO.Using the technique,a novel 2 488GHz of monolithical integrated injected synchronized ring VCO (ISRVCO) is realize...Oscillator IC technique is developed by combining injecting synchronization technique with a ring VCO.Using the technique,a novel 2 488GHz of monolithical integrated injected synchronized ring VCO (ISRVCO) is realized in a standard 0 25μm CMOS process.The ISRVCO is characterized by the following performances: -100dBc /Hz@1MHz at free running frequency,-91 7dBc/Hz@10kHz when injection is locked.With the 3 3V of power supply,the tuning range is 150MHz and the locking range is 100MHz with 50m V p p signal injection.展开更多
Collective unidirectional motion of an asymmetrically coupled array of oscillators in symmetric periodic potentials is studied. A directed current is observed when the drift coupling is presented, while no external bi...Collective unidirectional motion of an asymmetrically coupled array of oscillators in symmetric periodic potentials is studied. A directed current is observed when the drift coupling is presented, while no external biased force is applied. Negative directed current is found when varying system parameters. An addition of a periodic rocking force may enhance the efficiency of directed transport. Resonant steps of the current are found and interpreted as the mode locking between the array and the ac force. Noise-assisted transport is observed, and an optimal noise intensity can give rise to a most efficient transport. The directed transport thus can be optimized and furthermore controlled by suitably adjusting the parameters of the system.展开更多
By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes ...By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.展开更多
Rigid blocking masses are located in the typical base structure of a power cabin based on the impedance mismatch principle.By combining the acoustic-structural coupling method and statistical energy analysis,the full-...Rigid blocking masses are located in the typical base structure of a power cabin based on the impedance mismatch principle.By combining the acoustic-structural coupling method and statistical energy analysis,the full-band vibration and sound radiation reduction effect of vibration isolation masses located in a base structure was researched.The influence of the blocking mass’ cross-section size and shape parameters and the layout location of the base isolation performance was discussed.Furthermore,the effectiveness of rigid vibration isolation design of the base structure was validated.The results show that the medium and high frequency vibration and sound radiation of a power cabin are effectively reduced by a blocking mass.Concerning weight increment and section requirement,suitably increasing the blocking mass size and section height and reducing section width can result in an efficiency-cost ratio.展开更多
基金The National Natural Science Foundation of China(No. 60974116 )the Research Fund of Aeronautics Science (No.20090869007)Specialized Research Fund for the Doctoral Program of Higher Education (No. 200902861063)
文摘In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop （PLL） in frequency control and an automatic gain control （AGC） method in amplitude control. A digital processing circuit with a field programmable gate array （FPGA） is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.
文摘A new method for the control of the speed of an ultrasonic motor and its implementation are proposed. The method is merely used by detecting the time when motor′s monitor signal reaches a non zero reference value than a zero one, the direction, in which the driving frequency of the motor should be shifted, can be promptly calculated. With the aid of a CPU and the phase locked frequency doubling technique, the motor can be steadily driven in a wide range of frequency and the optimum frequency can be captured rapidly and precisely. Experiment shows that the above method is available.
文摘A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.
文摘A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.
文摘In this paper the method of multiple scales is used to study the nonlinear dynamics of the ice soil platform system. Results show that the system exhibits multiple kinds of combination resonances and that its natural frequencies accord with the testing results of the model platform. Under the condition of primary resonance,we discussed the nonlinear dynamic characteristics of self excited, locking,forced vibrations. They conform to the on site observation. This paper explains the ice induced vibration mechanism and thus establishes an appropriate mechanical model for the nonlinear analysis of the offshore platform systems.
文摘Several key techniques for a PLL-type frequency synthesizer for WLAN receivers are studied. Its structure is analyzed and the main parameters are proposed. A monolithic LC-tuned voltage controlled oscillator （LCVCO） with low phase noise is fabricated with TSMC 0.18μm RF （radio frequency） CMOS technology. The measured phase noise is - ll7dBc/Hz at 4MHz off the center frequency of 4. 189GHz. A down-scaling circuit with low power dissipation was fabricated in a TSMC 0.18μm mixed-signal CMOS process. The measured results show that the IC can work well under a 1.8V power supply. Its total power dissipation is only 13mW.
文摘An improved on-chip CMOS astable multivibrator is proposed, which overcomes the shortcomings of the traditional one that the signal duty-cycle is depending on model parameters, and generates stable clock signal with duty-cycle equaling 50%. The latch-up effect has been prevented on the improved circuit. It is extremely important that all the excellent performances of the improved astable multivibrator have been achieved with a dynamic power consumption equaling its predecessor one. The advantage of the structure has been verified by SPICE simulation.
文摘Oscillator IC technique is developed by combining injecting synchronization technique with a ring VCO.Using the technique,a novel 2 488GHz of monolithical integrated injected synchronized ring VCO (ISRVCO) is realized in a standard 0 25μm CMOS process.The ISRVCO is characterized by the following performances: -100dBc /Hz@1MHz at free running frequency,-91 7dBc/Hz@10kHz when injection is locked.With the 3 3V of power supply,the tuning range is 150MHz and the locking range is 100MHz with 50m V p p signal injection.
文摘Collective unidirectional motion of an asymmetrically coupled array of oscillators in symmetric periodic potentials is studied. A directed current is observed when the drift coupling is presented, while no external biased force is applied. Negative directed current is found when varying system parameters. An addition of a periodic rocking force may enhance the efficiency of directed transport. Resonant steps of the current are found and interpreted as the mode locking between the array and the ac force. Noise-assisted transport is observed, and an optimal noise intensity can give rise to a most efficient transport. The directed transport thus can be optimized and furthermore controlled by suitably adjusting the parameters of the system.
文摘By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.
基金Supported by the International Cooperation Program under Grant No.2007DFR80340the National Natural Science Foundation of China under Grant No.50779007
文摘Rigid blocking masses are located in the typical base structure of a power cabin based on the impedance mismatch principle.By combining the acoustic-structural coupling method and statistical energy analysis,the full-band vibration and sound radiation reduction effect of vibration isolation masses located in a base structure was researched.The influence of the blocking mass’ cross-section size and shape parameters and the layout location of the base isolation performance was discussed.Furthermore,the effectiveness of rigid vibration isolation design of the base structure was validated.The results show that the medium and high frequency vibration and sound radiation of a power cabin are effectively reduced by a blocking mass.Concerning weight increment and section requirement,suitably increasing the blocking mass size and section height and reducing section width can result in an efficiency-cost ratio.
