基于改进锁频器频率偏差检测的光伏逆变器快速频率响应控制

光伏电站高比例接入电网造成电力系统结构持续性改变,导致电网可调节资源存量不断下降,抵御故障扰动的能力减弱,电网频率越限风险增加。为提高光伏电站快速频率响应能力,本文根据现有新能源调频政策,设计了光伏逆变器有功-频率下垂特性,提出了基于改进二阶广义积分锁频器的光伏逆变器快速频率响应控制策略,使光伏逆变器具备主动调频的功能。采用改进二阶广义积分锁频器快速检测系统频率,并将频率偏差直接反馈给光伏逆变器控制系统,克服了传统锁相环在电网频率突变时相位偏差大、时延等问题。仿真和实验证明了光伏逆变器快速频率响应控制的正确性与可行性。

低信噪比下锁频锁相器性能分析及改进

针对锁频锁相器(Phase and Frequency Detector,PFD)应用于低信噪比、大频偏的条件,通过理论分析和仿真验证阐述了窗口类型对系统频偏捕获速度、范围、噪声门限及相位噪声抖动的影响机理.推导出等效相位噪声功率谱密度的表达式.证明了大窗口具有更低的噪声门限和更小的稳态相位抖动,但捕获速度较慢.为了提高捕获速度,对鉴相器输出值取极性运算得到改进的PFD算法.新算法不仅能增加鉴相增益提高捕获速度;还可以减少等效噪声功率谱密度降低相位抖动;同时新算法不需要乘法器便于硬件实现.最后新算法的性能通过仿真得到了验证.

A Low Jitter PLL in a 90nm CMOS Digital Process

A low jitter phase-locked loop （PLL） that does not need analog resistors and capacitors is designed and fabrica- ted in a 90nm CMOS digital process. The metal parasitic capacitor is used in the PLL loop filter. Test results show that when the PLL is locked on 1. 989GHz, the RMS jitter is 3. 7977ps, the peak-to-peak jitter is 31. 225ps, and the power con- sumption is about 9mW. The locked output frequency range is from 125MHz to 2.7GHz.

Fast-Lock Low-Jitter PLL with a Simple Phase-Frequency Detector

A fast-locking, low-jitter, phase-locked loop （PLL） with a simple phase-frequency detector is proposed. The phase-frequency detector is composed of only two XOR gates. It simultaneously achieves low jitter and short locking time. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45. The PLL is fabricated in 0. 1Stem CMOS technology. The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is - 102.6dBc/Hz. The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps. The power dissipation excluding the output buffers is only 21.6roW at a 1.8V supply.

A Novel Digital Transceiver for CT0 Standard

This paper introduces a novel digital transceiver for the cordless telephone zero （CT0） standard,which uses a digital modulation and demodulation technique to handle the signal instead of the traditional analog meth-od. In the transmitter,a fractional-N phase locked loop （PLL） is utilized to realize the continuous phase frequency shift key （CPFSK） modulation,and a 2 Ts raised cosine （2RC） shaping technique is used to reduce the occupied bandwidth. In the receiver,a novel digital method is proposed to demodulate the 2RC CPFSK signal. This chip is fabricated using an SMIC 0.35μm mixed signal CMOS process with a die size of 2mm × 2mm. With an external low noise amplifier （LNA）,the sensitivity of the chip is better than -103dBm.

Design of Down Scalers in Mixed-Signal GHz Frequency Synthesizer

An optimized method is presented to design the down scalers in a GHz frequency synthesizer. The down scalers are comprised of dual modulus prescaler （DMP） and programmable ＆ pulse swallow divider,different methods of high frequency analog circuit and digital logical synthesis are adopted respectively. Using a DMP high speed, lower jitter and lower power dissipation are obtained,and output frequency of 133.0MHz of the DMP working at divide-by-8 shows an RMS jitter less than 2ps. The flexibility and reusability of the progrs, mmable divider is high;its use could be extended to many complicated frequency synthesizers. By comparison,it is a better design on performance of high-frequency circuit and good design flexibility.

2.5Gb/s 0.18μm CMOS Clock and Data Recovery Circuit

A 2.5Gb/s clock and data recovery （CDR） circuit is designed and realized in TSMC＇s standard 0.18/μm CMOS process. The clock recovery is based on a PLL. For phase noise optimization,a dynamic phase and frequency detector （PFD） is used in the PLL. The rms jitter of the recovered 2.5GHz clock is 2.4ps and the SSB phase noise is - 111dBc/Hz at 10kHz offset. The rms jitter of the recovered 2.5Gb/s data is 3.3ps. The power consumption is 120mW.

A 2.4GHz Quadrature Output Frequency Synthesizer

A design and implementation for a 2.4GHz quadrature output frequency synthesizer intended for bluetooth in 0. 35μm CMOS technology are presented. A differentially controlled quadrature voltage-controlled oscillator （QVCO） is employed to generate quadrature （I/Q） signals. A second-order loop filter, with a unit gain transconductance amplifier having the performance of a third-order loop filter,is exploited for low cost. The measured spot phase noise is -106.15dBc/Hz@ 1MHz. Close-in phase noise is less than -70dBc/Hz. The synthesizer consumes 13.5mA under a 3.3V voltage supply. The core size is 1.3mm×0. 8mm.

A Fractional-N CMOS DPLL with Self-Calibration

A digital phase-locked loop （DPLL） based on a new digital phase-frequency detector is presented. The self-calibration technique is employed to acquire wide lock range,low jitter, and fast acquisition. The DPLL works from 60 to 600MHz at a supply voltage of 1.8V. It also features a fraetional-N synthesizer with digital 2nd-order sigma-delta noise shaping, which can achieve a short lock time,a high frequency resolution,and an improved phase-noise spectrum. The DPLL has been implemented in SMIC 0. 18μm 1.8V 1P6M CMOS technology. The peak-to-peak jitter is less than 0. 8% of the output clock period and the lock time is less than 150 times of the reference clock period after the pre-divider.

Low Jitter,Dual-Modulus Prescalers for RF Receivers

Dual-modulus prescalers （DMP） for RF receivers are studied. An improved D-latch is proposed to increase the speed and the driving capability of the DMP. A novel D-latch architecture integrated with ‘OR＇ logic is proposed to decrease the complexity of the circuit. A divided-by-16/17 DMP for application in a digital video broadcasting-terrestrial receiver is realized with a TSMC 0.18μm mixed-signal CMOS process. The programmable ＆ pulse swallow divider in this receiver is designed with a 0.18μm CMOS standard cell library and realized in the same process. The measured results show that the DMP has an output jitter of less than 0.03% and works well with the programmable ＆ pulse swallow divider.

A 900MHz CMOS PLL/Frequency Synthesizer Initialization Circuit

A 900MHz CMOS PLL/frequency synthesizer using current-adjustable charge-pump circuit and on-chip loop filter with initialization circuit is presented.The charge-pump current is insensitive to the changes of temperature and power supply.The value of the charge-pump current can be changed by switches,which are controlled by external signals.Thus the performance of the PLL,such as loop bandwidth,can be changed with the change of the charge-pump current.The loop filter initialization circuit can speed up the PLL when the power is on.A multi-modulus prescaler is used to fulfill the frequency synthesis.The circuit is designed using 0.18μm,1.8V,1P6M standard digital CMOS process.

A Σ-Δ Fractional-N PLL Frequency Synthesizer with AFC for SRD Applications

A fractional-N frequency synthesizer for 433/868MHz SRD applications is implemented in a 0.3μm CMOS process. A wide-band VCO and an AFC are used to cover the desired bands. A 3bit third order sigma-delta modulator is adopted to reduce the out-band phase noise. The measurements show a VCO tuning range from 1.31 to 1.88GHz with AFC working correctly,an out-band phase noise of -139dBc/Hz at 3MHz offset frequency, and a fractional spur of less than - 60dBc. The chip area is 1.5mm × 1.2mm and the total current dissipation including LO buffers is 19mA from a single 3.0V supply voltage.

The Jitter Performance Comparison Between DLL and PLL-Based RF CMOS Oscillators

By jitter performance comparison between PLL (Phase Locked Loop) and DLL (Delay Locked Loop),a helpful equation is derived for the structure choice between DLL and PLL based synthesizers fabricated in CMOS processes to get an optimum jitter performance and power consumption.For a frequency synthesizer,a large multiple factor prefers PLL based configuration which consumes less power,while a small one needs DLL based topology which produces a better jitter performance.

A virtual lock-in amplifier,spectrum analyzer,impedance meter and semiconductor analyzer implemented on an SR7265 hardware target

Lock-in amplifiers are used to detect and measure very small alternating current(AC)signals down to the range of nVs.Accurate measurements can be made even when the small signals are buried by noise thousands of times larger.With the digital signal processing(DSP)technology involved in modern instrumentation,a lock-in amplifier is more versatile in sensing and recovering small signals.Combining the virtual instrumentation technology,we reorganize the functional blocks of a programmable lock-in amplifier and build it as a virtual spectrum analyzer,virtual impedance meter,virtual network analyzer,virtual semiconductor parameter analyzer,signal generator,etc.A 4 layer model is used to implement these virtual instruments.The same virtual instrument can also be implemented on a general purpose FPGA developing board.

COMPARISON OF SIGMA-DELTA MODULATOR FOR FRACTIONAL-N PLL FREQUENCY SYNTHESIZER

This paper investigates the design of digital Sigma-Delta Modulator (SDM) for fractional-N frequency synthesizer. Characteristics of SDMs are compared through theory analysis and simulation. The curve of maximum-loop-bandwidth vs. maximum-phase-noise is suggested to be a new criterion to the performance of SDM,which greatly helps designers to select an appropriate SDM structure to meet their real application requirements and to reduce the cost as low as possible. A low-spur 3-order Mul-tistage Noise Shaping (MASH)-1-1-1 SDM using three 2-bit first-order cascaded modulators is proposed,which balances the requirements of tone-free and maximum operation frequency.

Effects of Interfaces on Dynamics in Micro-Fluidic Devices：Slip-Boundaries' Impact on Rotation Characteristics of Polar Liquid Film Motors

A new approach for exploring effects of interfaces on polar liquids is presented. Their impact on the polar liquid film motor(PLFM) – a novel micro-fluidic device – is studied. We account for the interface's impact by modeling slip boundary effects on the PLFM's electro-hydro-dynamical rotations. Our analytical results show as k = l_s/R increases(with ls denoting the slip length resulting from the interface's impact on the film's properties, k >-1 and R denoting the film's radius):(a) PLFMs subsequently exhibit rotation characteristics under "negative-", "no-", "partial-" and"perfect-" slip boundary conditions;(b) The maximum value of the linear velocity of the steady rotating film increases linearly and its location approaches the film's border;(c) The decay of the angular velocities' dependency on the distance from the center of the film slows down, resulting in a macroscopic flow near the boundary. With our calculated rotation speed distributions consistent with the existing experimental ones, research aiming at fitting computed to measured distributions promises identifying the factors affecting ls, e.g., solid-fluid potential interactions and surface roughness.The consistency also is advantageous for optimizing PLFM's applications as micro-washers, centrifuges, mixers in the lab-on-a-chip.