A novel method to characterize CMOS process fluctuations in subthreshold current mirrors （SCM） is reported. The proposed model is succinct in methodology and calculation complexity compared with previous statistical...A novel method to characterize CMOS process fluctuations in subthreshold current mirrors （SCM） is reported. The proposed model is succinct in methodology and calculation complexity compared with previous statistical models. However,it provides favorable estimations of CMOS process fluctuations on the SCM circuit, which makes it promising for engineering applications. The model statistically abstracts physical parameters, which depend on the IC process, into random variables with certain mean values and standard deviations, while aggregating all the random impacts into a discrete martingale. The correctness of the proposed method is experimentally verified on an SCM circuit implemented in an SMIC 0.18μm CMOS 1P6M mixed signal process with a conversion factor of 100 in an input range from 100pA to lμA. The pro- posed theory successfully predicts - 10% of die-to-die fluctuation measured in the experiment, and also suggests the -lmV of threshold voltage standard deviation over a single die,which meets the process parameters suggested by the design kit from the foundry. The deviations between calculated probabilities and measured data are less than 8%. Meanwhile, pertinent suggestions concerning high fluctuation tolerance subthreshold analog circuit design are also made and discussed.展开更多
Studies on first GaN-based blue-violet laser diodes(LDs) in China mainland are reported.High quality GaN materials as well as GaN-based quantum wells laser structures are grown by metal-organic chemical vapor depositi...Studies on first GaN-based blue-violet laser diodes(LDs) in China mainland are reported.High quality GaN materials as well as GaN-based quantum wells laser structures are grown by metal-organic chemical vapor deposition method.The X-ray double-crystal diffraction rocking curve measurements show the full-width half maximum of 180″ and 185″ for (0002) symmetric reflection and (10 12) skew reflection,respectively.A room temperature mobility of 850cm2/(V·s) is obtained for a 3μm thick GaN film.Gain guided and ridge geometry waveguide laser diodes are fabricated with cleaved facet mirrors at room temperature under pulse current injection.The lasing wavelength is 405 9nm.A threshold current density of 5kA/cm2 and an output light power over 100mW are obtained for ridge geometry waveguide laser diodes.展开更多
The relationship between the thermal/electrical conductivity enhancement in graphite nanoplatelets （GNPs） composites and the properties of filling graphite nanoplatelets is studied. The effective thermal and electri...The relationship between the thermal/electrical conductivity enhancement in graphite nanoplatelets （GNPs） composites and the properties of filling graphite nanoplatelets is studied. The effective thermal and electrical conductivity enhancements of GNP-oil nanofluids and GNP-polyimide composites are measured. By taking into account the particle shape, the volume fraction, the thermal conductivity of filling particles and the base fluids, the thermal and electrical conductivity enhancements of GNP nanofluids are theoretically predicted by the generalized effective medium theory. Both the nonlinear dependence of effective thermal conductivity on the GNP volume fraction in nanofhiids and the very low percolation threshold for GNP-polyimide composites are well predicted. The theoretical predications are found to be in reasonably good agreement with the experimental data. The generalized effective medium theory can be used for predicting the thermal and electrical properties of GNP composites and it is still available for most of the thermal/electrical modifications in two-phase composites.展开更多
A novel fully-depleted dual-gate MOSFET with a hetero-material gate and a lightly-doped drain is proposed. The hetero-material gate, which consists of a main gate and two side-gates,is used to control the surface pote...A novel fully-depleted dual-gate MOSFET with a hetero-material gate and a lightly-doped drain is proposed. The hetero-material gate, which consists of a main gate and two side-gates,is used to control the surface potential distribution. The fabrication process and the device characteristics are simulated with Tsuprem-4 and Medici separately. Compared to a common DG fully depleted SO1 MOSFET,the proposed device has much higher on/off current ratio and superior sub-threshold slope. The on/off current ratio is about 10^10 and the sub-threshold slope is nearly 60mV/dec under a 0.18μm process.展开更多
Time-dependent thermal simulation of ridge-geometry InGaN laser diodes is carried out with a two-dimensional model. A high temperature in the waveguide layer and a large temperature step between the regions under and ...Time-dependent thermal simulation of ridge-geometry InGaN laser diodes is carried out with a two-dimensional model. A high temperature in the waveguide layer and a large temperature step between the regions under and outside the ridge are generated due to the poor thermal conductivity of the sapphire substrate and the large threshold current and voltage. The temperature step is thought to have a strong influence on the characteristics of the laser diodes. Time-resolved measurements of light-current curves,spectra, and the far-field pattern of the InGaN laser diodes under pulsed operation are performed. The results show that the thermal lensing effect improves the confinement of the higher order modes and leads to a lower threshold current and a higher slope efficiency of the device while the high temperature in the active layer results in a drastic decrease in the slope efficiency.展开更多
A CMOS voltage reference, which is based on VGs and/x ΔGS in the weak inversion region, has been designed and implemented in standard 0.6μm CMOS technology. No diodes and parasitic bipolar junction transistors （BJT...A CMOS voltage reference, which is based on VGs and/x ΔGS in the weak inversion region, has been designed and implemented in standard 0.6μm CMOS technology. No diodes and parasitic bipolar junction transistors （BJTs） are used. The proposed voltage reference uses a current-mode topology by summing a PTAT current and a CTAT current into a re- sistor to generate the required reference voltage. It can also provide more than one reference voltage output, which is quite suitable for systems requiring many different reference voltages simultaneously. The occupied chip area is 0. 023mm^-2 . The operation supply voltage is from 2.5 to 6V, and the maximum supply current is 8.25μA. The designed three different out- puts are respectively about 203mV, 1.0V, and 2.05V at room temperature when the supply voltage is 4V. The circuit achieves a temperature coefficient of 31ppm/℃ in the temperature range of 0 to 100℃ and an average line regulation of ± 0. 203%/V. The voltage reference has been successfully applied in a white LED backlight driver chip.展开更多
A simple new method based on the measurement of charge pumping technique is proposed to separate and quantify experimentally the effects of oxide-trapped charges and interface-trapped charges on threshold voltage degr...A simple new method based on the measurement of charge pumping technique is proposed to separate and quantify experimentally the effects of oxide-trapped charges and interface-trapped charges on threshold voltage degradation in p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) under hot-carrier stress.Further,the experimental results verify the validness of this method.It is shown that,all three mechanisms of electron trapping effect,hole trapping effect and interface trap generation play important roles in p-channel MOSFETs degradation.It is noted that interface-trapped charge is still the dominant mechanism for hot-carrier-induced degradation in p-channel MOSFETs,while a significant contribution of oxide-trapped charge to threshold voltage is demonstrated and quantified.展开更多
A dual material gate silicon-on-insulator MOSFET with asymmetrical halo is presented to improve short channel effect and carder transport efficiency for the first time. The front gate consists of two metal gates with ...A dual material gate silicon-on-insulator MOSFET with asymmetrical halo is presented to improve short channel effect and carder transport efficiency for the first time. The front gate consists of two metal gates with different work functions by making them contacting laterally, and the channel is more heavily doped near the source than in the rest. Using a three-region polynomial potential distribution and a universal boundary condition, a two-dimensional analytical model for the fully depleted silicon-on-insulator MOSFET is developed based on the explicit solution of two-dimensional Poisson＇s equation. The model includes the calculation of potential distribution along the channel and subthreshold current. The performance improvement of the novel silicon-on-insulator MOSFET is examined and compared with the traditional silicon-on-insulator MOSFET using the analytical model and two-dimensional device simulator MEDICI. It is found that the novel silicon-on-insulator MOSFET could not only suppress short channel effect, but also increase cartier transoort efficiency noticeably. The derived analytical model agrees well with MEDICI.展开更多
Considering the effect of temperature and process variations, the inputs and clock signals combination sleep state dependent leakage current characteristics is analyzed and the optimal sleep state is examined in sub-6...Considering the effect of temperature and process variations, the inputs and clock signals combination sleep state dependent leakage current characteristics is analyzed and the optimal sleep state is examined in sub-65nm dual threshold voltage （V1） footed domino circuits. HSPICE simulations based on 65nm and 45nm BSIM4 models show that the proposed CLIL state （the clock signal and inputs are all low） is the optimal state to reduce the leakage current of the high fan-in footed domino circuits at high temperature and almost all footed domino circuits at room temperature, as compared to the conventional CHIL state （the clock signal is high and inputs are all low） and the CHIH state （the clock signal and inputs are all high）. Further, the influence of the process variations on the leakage current characteristics of the dual V1 footed domino circuits is evaluated. At last, temperature and process variation aware new low leakage current setup guidelines are provided.展开更多
文摘A novel method to characterize CMOS process fluctuations in subthreshold current mirrors （SCM） is reported. The proposed model is succinct in methodology and calculation complexity compared with previous statistical models. However,it provides favorable estimations of CMOS process fluctuations on the SCM circuit, which makes it promising for engineering applications. The model statistically abstracts physical parameters, which depend on the IC process, into random variables with certain mean values and standard deviations, while aggregating all the random impacts into a discrete martingale. The correctness of the proposed method is experimentally verified on an SCM circuit implemented in an SMIC 0.18μm CMOS 1P6M mixed signal process with a conversion factor of 100 in an input range from 100pA to lμA. The pro- posed theory successfully predicts - 10% of die-to-die fluctuation measured in the experiment, and also suggests the -lmV of threshold voltage standard deviation over a single die,which meets the process parameters suggested by the design kit from the foundry. The deviations between calculated probabilities and measured data are less than 8%. Meanwhile, pertinent suggestions concerning high fluctuation tolerance subthreshold analog circuit design are also made and discussed.
文摘Studies on first GaN-based blue-violet laser diodes(LDs) in China mainland are reported.High quality GaN materials as well as GaN-based quantum wells laser structures are grown by metal-organic chemical vapor deposition method.The X-ray double-crystal diffraction rocking curve measurements show the full-width half maximum of 180″ and 185″ for (0002) symmetric reflection and (10 12) skew reflection,respectively.A room temperature mobility of 850cm2/(V·s) is obtained for a 3μm thick GaN film.Gain guided and ridge geometry waveguide laser diodes are fabricated with cleaved facet mirrors at room temperature under pulse current injection.The lasing wavelength is 405 9nm.A threshold current density of 5kA/cm2 and an output light power over 100mW are obtained for ridge geometry waveguide laser diodes.
基金The National Natural Science Foundation of China(No.50906073,31070517)China Postdoctoral Science Foundation(No.20110491332)+1 种基金Jiangsu Planned Projects for Postdoctoral Research Funds(No.1101009B)the Science and Technology Development Plan of North Jiangsu(No.BC2012444)
文摘The relationship between the thermal/electrical conductivity enhancement in graphite nanoplatelets （GNPs） composites and the properties of filling graphite nanoplatelets is studied. The effective thermal and electrical conductivity enhancements of GNP-oil nanofluids and GNP-polyimide composites are measured. By taking into account the particle shape, the volume fraction, the thermal conductivity of filling particles and the base fluids, the thermal and electrical conductivity enhancements of GNP nanofluids are theoretically predicted by the generalized effective medium theory. Both the nonlinear dependence of effective thermal conductivity on the GNP volume fraction in nanofhiids and the very low percolation threshold for GNP-polyimide composites are well predicted. The theoretical predications are found to be in reasonably good agreement with the experimental data. The generalized effective medium theory can be used for predicting the thermal and electrical properties of GNP composites and it is still available for most of the thermal/electrical modifications in two-phase composites.
文摘A novel fully-depleted dual-gate MOSFET with a hetero-material gate and a lightly-doped drain is proposed. The hetero-material gate, which consists of a main gate and two side-gates,is used to control the surface potential distribution. The fabrication process and the device characteristics are simulated with Tsuprem-4 and Medici separately. Compared to a common DG fully depleted SO1 MOSFET,the proposed device has much higher on/off current ratio and superior sub-threshold slope. The on/off current ratio is about 10^10 and the sub-threshold slope is nearly 60mV/dec under a 0.18μm process.
文摘Time-dependent thermal simulation of ridge-geometry InGaN laser diodes is carried out with a two-dimensional model. A high temperature in the waveguide layer and a large temperature step between the regions under and outside the ridge are generated due to the poor thermal conductivity of the sapphire substrate and the large threshold current and voltage. The temperature step is thought to have a strong influence on the characteristics of the laser diodes. Time-resolved measurements of light-current curves,spectra, and the far-field pattern of the InGaN laser diodes under pulsed operation are performed. The results show that the thermal lensing effect improves the confinement of the higher order modes and leads to a lower threshold current and a higher slope efficiency of the device while the high temperature in the active layer results in a drastic decrease in the slope efficiency.
文摘A CMOS voltage reference, which is based on VGs and/x ΔGS in the weak inversion region, has been designed and implemented in standard 0.6μm CMOS technology. No diodes and parasitic bipolar junction transistors （BJTs） are used. The proposed voltage reference uses a current-mode topology by summing a PTAT current and a CTAT current into a re- sistor to generate the required reference voltage. It can also provide more than one reference voltage output, which is quite suitable for systems requiring many different reference voltages simultaneously. The occupied chip area is 0. 023mm^-2 . The operation supply voltage is from 2.5 to 6V, and the maximum supply current is 8.25μA. The designed three different out- puts are respectively about 203mV, 1.0V, and 2.05V at room temperature when the supply voltage is 4V. The circuit achieves a temperature coefficient of 31ppm/℃ in the temperature range of 0 to 100℃ and an average line regulation of ± 0. 203%/V. The voltage reference has been successfully applied in a white LED backlight driver chip.
文摘A simple new method based on the measurement of charge pumping technique is proposed to separate and quantify experimentally the effects of oxide-trapped charges and interface-trapped charges on threshold voltage degradation in p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) under hot-carrier stress.Further,the experimental results verify the validness of this method.It is shown that,all three mechanisms of electron trapping effect,hole trapping effect and interface trap generation play important roles in p-channel MOSFETs degradation.It is noted that interface-trapped charge is still the dominant mechanism for hot-carrier-induced degradation in p-channel MOSFETs,while a significant contribution of oxide-trapped charge to threshold voltage is demonstrated and quantified.
基金Project 60472003 supported by National Natural Science Foundation of China and 2005CB321701 by the State Key Development Program for BasicResearch of China
文摘A dual material gate silicon-on-insulator MOSFET with asymmetrical halo is presented to improve short channel effect and carder transport efficiency for the first time. The front gate consists of two metal gates with different work functions by making them contacting laterally, and the channel is more heavily doped near the source than in the rest. Using a three-region polynomial potential distribution and a universal boundary condition, a two-dimensional analytical model for the fully depleted silicon-on-insulator MOSFET is developed based on the explicit solution of two-dimensional Poisson＇s equation. The model includes the calculation of potential distribution along the channel and subthreshold current. The performance improvement of the novel silicon-on-insulator MOSFET is examined and compared with the traditional silicon-on-insulator MOSFET using the analytical model and two-dimensional device simulator MEDICI. It is found that the novel silicon-on-insulator MOSFET could not only suppress short channel effect, but also increase cartier transoort efficiency noticeably. The derived analytical model agrees well with MEDICI.
基金supported by the2008Science and Research Foundation of Hebei Education Depart ment(No.2008308)~~
文摘Considering the effect of temperature and process variations, the inputs and clock signals combination sleep state dependent leakage current characteristics is analyzed and the optimal sleep state is examined in sub-65nm dual threshold voltage （V1） footed domino circuits. HSPICE simulations based on 65nm and 45nm BSIM4 models show that the proposed CLIL state （the clock signal and inputs are all low） is the optimal state to reduce the leakage current of the high fan-in footed domino circuits at high temperature and almost all footed domino circuits at room temperature, as compared to the conventional CHIL state （the clock signal is high and inputs are all low） and the CHIH state （the clock signal and inputs are all high）. Further, the influence of the process variations on the leakage current characteristics of the dual V1 footed domino circuits is evaluated. At last, temperature and process variation aware new low leakage current setup guidelines are provided.
