A novel SPIC(smart power IC) with a simple APFC(active power factor correction) circuit on one chip is proposed.The V _ bus (bus voltage) with high power factor falls from 600V to 400V by using a delay circuit in w...A novel SPIC(smart power IC) with a simple APFC(active power factor correction) circuit on one chip is proposed.The V _ bus (bus voltage) with high power factor falls from 600V to 400V by using a delay circuit in which a long channel length NMOS is used to substitute a large biasing resistance to save chip area.The lower V _ bus results in a smaller R _ on (on-resistance) of power switcher,which reduces the power loss of the power devices,improves the efficiency of the circuit,and reduces the cost of circuits.An integrated high voltage over voltage protect circuit is also designed in the circuits.Theory and simulations both prove the correctness and availability of the design.展开更多
An efficient parallel global router using random optimization that is independent of net ordering is proposed.Parallel approaches are described and strategies guaranteeing the routing quality are discussed.The wire le...An efficient parallel global router using random optimization that is independent of net ordering is proposed.Parallel approaches are described and strategies guaranteeing the routing quality are discussed.The wire length model is implemented on multiprocessor,which enables the algorithm to approach feasibility of large scale problems.Timing driven model on multiprocessor and wire length model on distributed processors are also presented.The parallel algorithm greatly reduces the run time of routing.The experimental results show good speedups with no degradation of the routing quality.展开更多
A lumped π-type equivalent circuit of planar spiral inductor for CMOS RFIC application is developed by the domain decomposition method for conformal modules （DDM-CM）. Closed form expressions of lumped parameters fo...A lumped π-type equivalent circuit of planar spiral inductor for CMOS RFIC application is developed by the domain decomposition method for conformal modules （DDM-CM）. Closed form expressions of lumped parameters for a square spiral inductor on a Si-SiO2 substrate are obtained and verified with the previously published experimental results.展开更多
文摘A novel SPIC(smart power IC) with a simple APFC(active power factor correction) circuit on one chip is proposed.The V _ bus (bus voltage) with high power factor falls from 600V to 400V by using a delay circuit in which a long channel length NMOS is used to substitute a large biasing resistance to save chip area.The lower V _ bus results in a smaller R _ on (on-resistance) of power switcher,which reduces the power loss of the power devices,improves the efficiency of the circuit,and reduces the cost of circuits.An integrated high voltage over voltage protect circuit is also designed in the circuits.Theory and simulations both prove the correctness and availability of the design.
文摘An efficient parallel global router using random optimization that is independent of net ordering is proposed.Parallel approaches are described and strategies guaranteeing the routing quality are discussed.The wire length model is implemented on multiprocessor,which enables the algorithm to approach feasibility of large scale problems.Timing driven model on multiprocessor and wire length model on distributed processors are also presented.The parallel algorithm greatly reduces the run time of routing.The experimental results show good speedups with no degradation of the routing quality.
文摘A lumped π-type equivalent circuit of planar spiral inductor for CMOS RFIC application is developed by the domain decomposition method for conformal modules （DDM-CM）. Closed form expressions of lumped parameters for a square spiral inductor on a Si-SiO2 substrate are obtained and verified with the previously published experimental results.
