期刊文献+
共找到5篇文章
< 1 >
每页显示 20 50 100
RS-232C串口红外数据传输系统 被引量:2
1
作者 金明亮 游大海 黄上游 《电子产品世界》 2003年第12A期27-29,共3页
本文给出在RS-232C串口间实现红外无线数据传输的方案,载波由555定时器产生并实现数据调制。采用一体化集成接收电路完成数据解调,同时分析解决了误码问题,给出了详细的电路图。
关键词 RS-232C 红外无线数据传输 555定时器 误码 集成接收电路
下载PDF
Sensitivity Design for a CMOS Optoelectronic Integrated Circuit Receiver
2
作者 朱浩波 毛陆虹 +1 位作者 余长亮 马利远 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2007年第5期676-680,共5页
A sensitivity design method for a CMOS optoelectronic integrated circuit (OEIC) receiver is reported. The receiver consists of a regulated cascade (RGC) transimpedance amplifier (TIA) and a double photodiode (... A sensitivity design method for a CMOS optoelectronic integrated circuit (OEIC) receiver is reported. The receiver consists of a regulated cascade (RGC) transimpedance amplifier (TIA) and a double photodiode (DPD) detector. The noise and sensitivity of the receiver are analyzed in detail. The noise mainly comes from the thermal noise of resistors and the flicker noise of MOSFETs. The relationship between noise and receiver sensitivity is presented. The sensitivity design method for the receiver is given by a set of equations. The OEIC receiver was implemented in a CSMC 0.6μm standard CMOS process. The measured eye diagram shows that the CMOS OEIC receiver is able to work at bit rates of up to 1.25GB/s and the sensitivity is - 12dBm. 展开更多
关键词 CMOS OEIC RECEIVER sensitivity noise
下载PDF
Bandwidth Design for CMOS Monolithic Photoreceiver
3
作者 粘华 毛陆虹 +2 位作者 李炜 陈弘达 贾久春 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2005年第4期677-682,共6页
A monolithic photoreceiver which consists of a double photodiode (DPD) detector and a regulated cascade (RGC) transimpedance amplifier (TIA) is designed.The small signal circuit model of DPD is given and the bandwidth... A monolithic photoreceiver which consists of a double photodiode (DPD) detector and a regulated cascade (RGC) transimpedance amplifier (TIA) is designed.The small signal circuit model of DPD is given and the bandwidth design method of a monolithic photoreceiver is presented.An important factor which limits the bandwidth of DPD detector and the photoreceiver is presented and analyzed in detail.A monolithic photoreceiver with 1.71GHz bandwidth and 49dB transimpedance gain is designed and simulated by applying a low-cost 0.6μm CMOS process and the test result is given. 展开更多
关键词 double photodiode optoelectronics integrated circuit PHOTORECEIVER
下载PDF
Monolithically Integrated Optoelectronic Receivers Implemented in 0.25μm MS/RF CMOS
4
作者 陈弘达 高鹏 +1 位作者 毛陆虹 黄家乐 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2006年第2期323-327,共5页
A monolithically integrated optoelectronic receiver is presented. A silicon-based photo-diode and receiver circuits are integrated on identical substrates in order to eliminate the parasitics induced by hybrid packagi... A monolithically integrated optoelectronic receiver is presented. A silicon-based photo-diode and receiver circuits are integrated on identical substrates in order to eliminate the parasitics induced by hybrid packaging. Implemented in the present deep sub-micron MS/RF (mixed signal, radio frequency) CMOS,this monolithically OEIC takes advantage of several new features to improve the performance of the photo-diode and eventually the whole OEIC. 展开更多
关键词 monolithically integrated OEIC CMOS process
下载PDF
A Low-Voltage,Low-Power CMOS High Dynamic Range dB-Linear VGA for Super Heterodyne Receivers 被引量:3
5
作者 董桥 耿莉 邵志标 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2007年第11期1690-1695,共6页
This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled g... This paper presents a low-voltage low-power variable gain amplifier,which is applied in the automatic gain control loop of a super heterodyne receiver. Six stages are cascaded to provide an 81dB digitally controlled gain range in a 3dB step. The gain step error is less than 0.5dB. It operates at an intermediate frequency of 300kHz, and the power consumption is 1.35mW from a 1.8V supply. The prototype chip is implemented in a TSMC's 0.18μm 1P6M CMOS process and occupies approximately 0.24mm^2 . It is very suitable for portable wire- less communication systems. The measurement results agree well with the system requirements. 展开更多
关键词 variable gain amplifier low voltage low power super heterodyne receiver CMOS RF integratedcircuits
下载PDF
上一页 1 下一页 到第
使用帮助 返回顶部