为抑制半开绕组直线电机系统零序电流的产生,提出了一种基于逆变器非线性补偿的半开绕组直线电机系统的直接推力控制(direct thrust force control,DTFC)。首先,对半开绕组直线电机零序电流的运行机理进行了分析;其次,设计了基于新型开...为抑制半开绕组直线电机系统零序电流的产生,提出了一种基于逆变器非线性补偿的半开绕组直线电机系统的直接推力控制(direct thrust force control,DTFC)。首先,对半开绕组直线电机零序电流的运行机理进行了分析;其次,设计了基于新型开关表的DTFC策略;然后,引入了逆变器非线性补偿;最后,对所提DTFC进行了仿真验证。仿真结果表明,所提DTFC能明显抑制零序电流的产生,提高半开绕组直线电机系统的运行效率。其零序电流抑制性能系数约为0.07,不仅具备良好的稳态性能,同时还拥有优越的自启动性能与瞬态性能。展开更多
The objective of this research is to realize a composite nonlinear feedback control approach for a class of linear and nonlinear systems with parallel-distributed compensation along with sliding mode control technique...The objective of this research is to realize a composite nonlinear feedback control approach for a class of linear and nonlinear systems with parallel-distributed compensation along with sliding mode control technique.The proposed composite nonlinear feedback control approach consists of two parts.In a word,the first part provides the stability of the closed-loop system and the fast convergence response,as long as the second one improves transient response.In this research,the genetic algorithm in line with the fuzzy logic is designed to calculate constant controller coefficients and optimize the control effort.The effectiveness of the proposed design is demonstrated by servo position control system and inverted pendulum system with DC motor simulation results.展开更多
A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase...A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.展开更多
As a typical implementation of the probability hypothesis density(PHD) filter, sequential Monte Carlo PHD(SMC-PHD) is widely employed in highly nonlinear systems. However, the particle impoverishment problem introduce...As a typical implementation of the probability hypothesis density(PHD) filter, sequential Monte Carlo PHD(SMC-PHD) is widely employed in highly nonlinear systems. However, the particle impoverishment problem introduced by the resampling step, together with the high computational burden problem, may lead to performance degradation and restrain the use of SMC-PHD filter in practical applications. In this work, a novel SMC-PHD filter based on particle compensation is proposed to solve above problems. Firstly, according to a comprehensive analysis on the particle impoverishment problem, a new particle generating mechanism is developed to compensate the particles. Then, all the particles are integrated into the SMC-PHD filter framework. Simulation results demonstrate that, in comparison with the SMC-PHD filter, proposed PC-SMC-PHD filter is capable of overcoming the particle impoverishment problem, as well as improving the processing rate for a certain tracking accuracy in different scenarios.展开更多
文摘为抑制半开绕组直线电机系统零序电流的产生,提出了一种基于逆变器非线性补偿的半开绕组直线电机系统的直接推力控制(direct thrust force control,DTFC)。首先,对半开绕组直线电机零序电流的运行机理进行了分析;其次,设计了基于新型开关表的DTFC策略;然后,引入了逆变器非线性补偿;最后,对所提DTFC进行了仿真验证。仿真结果表明,所提DTFC能明显抑制零序电流的产生,提高半开绕组直线电机系统的运行效率。其零序电流抑制性能系数约为0.07,不仅具备良好的稳态性能,同时还拥有优越的自启动性能与瞬态性能。
文摘The objective of this research is to realize a composite nonlinear feedback control approach for a class of linear and nonlinear systems with parallel-distributed compensation along with sliding mode control technique.The proposed composite nonlinear feedback control approach consists of two parts.In a word,the first part provides the stability of the closed-loop system and the fast convergence response,as long as the second one improves transient response.In this research,the genetic algorithm in line with the fuzzy logic is designed to calculate constant controller coefficients and optimize the control effort.The effectiveness of the proposed design is demonstrated by servo position control system and inverted pendulum system with DC motor simulation results.
基金Supported by National Natural Science Foundation of China (No.60806010,No.60976030)
文摘A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.
基金Projects(61671462,61471383,61671463,61304103)supported by the National Natural Science Foundation of ChinaProject(ZR2012FQ004)supported by the Natural Science Foundation of Shandong Province,China
文摘As a typical implementation of the probability hypothesis density(PHD) filter, sequential Monte Carlo PHD(SMC-PHD) is widely employed in highly nonlinear systems. However, the particle impoverishment problem introduced by the resampling step, together with the high computational burden problem, may lead to performance degradation and restrain the use of SMC-PHD filter in practical applications. In this work, a novel SMC-PHD filter based on particle compensation is proposed to solve above problems. Firstly, according to a comprehensive analysis on the particle impoverishment problem, a new particle generating mechanism is developed to compensate the particles. Then, all the particles are integrated into the SMC-PHD filter framework. Simulation results demonstrate that, in comparison with the SMC-PHD filter, proposed PC-SMC-PHD filter is capable of overcoming the particle impoverishment problem, as well as improving the processing rate for a certain tracking accuracy in different scenarios.
