A low-voltage, low-power, and high-gain rail-to-rail operational amplifier （OpAmp） is presented. The replica-amplifier gain enhancement technique is applied to improve the DC gain of the amplifier, which does not de...A low-voltage, low-power, and high-gain rail-to-rail operational amplifier （OpAmp） is presented. The replica-amplifier gain enhancement technique is applied to improve the DC gain of the amplifier, which does not degrade the output swing and is very suitable for low-voltage applications. In a 0. 18/μm standard CMOS process,a 1V OpAmp with rail-to-rail output is designed. For a load capacitance of 5 pF,simulation by HSPICE shows that this OpAmp achieves an effective open-loop DC gain of 65. 9dB,gain bandwidth of 70.28 MHz,and phase margin of 50 with a quiescent power dissipation of 156.7μW.展开更多
A novel topology low-voltage high precision current reference based on subthreshold Metal-Oxide-Semiconductor Field Effect Transistors （MOSFETs） is presented. The circuit achieves a temperature-independent reference...A novel topology low-voltage high precision current reference based on subthreshold Metal-Oxide-Semiconductor Field Effect Transistors （MOSFETs） is presented. The circuit achieves a temperature-independent reference current by a proper combination current of two first-order temperature-compensation current references, which exploit the temperature characteristics of integrated poly2 resistors and the 1- V transconductance characteristics of MOSFET operating in the subthreshold region. The circuit, designed with the 1 st silicon 0.35 μm standard CMOS logic process technology, exhibits a stable current of about 2.25 μA with much low temperature coefficient of 3 × 10^-4μA/℃ in the temperature range of-40-150 ℃ at 1 V supply voltage, and also achieves a better power supply rejection ratio （PSRR） over a broad frequency. The PSRR is about -78 dB at DC and remains -42 dB at the frequency higher than 10 MHz. The maximal process error is about 6,7% based on the Monte Carlo simulation. So it has good process compatibility.展开更多
Sodium-ion batteries （NIBs） show great prospect on the energy storage applications benefiting from thei low cost and the abundant Na resources despite the expected lower energy density compared wit lithium-ion batte...Sodium-ion batteries （NIBs） show great prospect on the energy storage applications benefiting from thei low cost and the abundant Na resources despite the expected lower energy density compared wit lithium-ion batteries （LIBs）. To further enhance the competitive advantage, especially in energy densit3 developing the high-capacity carbon anode materials can be one of the effective approaches to realiz this goal. Herein, we report a novel carbon anode made from charcoal with a high capacity of ~400 Ah g i, wherein about 85% （〉330 mAh g^-1） of its total capacity is derived from the long plateau regio below ~0.1 V. which differs fiom those of typical hard carbon materials （~300 mAh g^-l） in NIBs but i similar to the graphite anode in LIBs. When coupled with air-stable Nao.gCuo.22Feo.3oMno.4802 oxid cathode, a high-energy density of ~240 Wh kg^-1 is achieved with good rate capability and cyclin stability. The discovery of this promising carbon anode is expected to further improve the energy densit of NIBs towards large-scale electrical energy storage.展开更多
We herein report the effective performance enhancement of the pentacene-based organic thin film transistors with silicon di- oxide dielectric by inserting a thin metal phthalocyanines interlayer between Au source/drai...We herein report the effective performance enhancement of the pentacene-based organic thin film transistors with silicon di- oxide dielectric by inserting a thin metal phthalocyanines interlayer between Au source/drain electrodes and the pentacene active layer. The threshold voltage decreased remarkably from ca. -20 V to a few volts （below -7.6 V） while the mobility in- creased 1.5-3 times after the insertion of the interlayer of only ca. 2 nm, which could be attributed to the reduction of the car- tier injection barrier. The results suggest a simple and effective way to achieve low-threshold-voltage pentacene-based organic thin film transistors with high mobility on silicon dioxide dielectric.展开更多
In this paper, performance of PECVD SiO 2 /Si 3 N 4 double layers electrets with different thicknesses were investigated detailedly in respect of chargeability, storage charge stability in high temperature and reliabi...In this paper, performance of PECVD SiO 2 /Si 3 N 4 double layers electrets with different thicknesses were investigated detailedly in respect of chargeability, storage charge stability in high temperature and reliability in high humidity environment. Samples with different thicknesses of Si 3 N 4 and SiO 2 were prepared on Pyrex 7740 glass substrates and characterized by isothermal and high humidity charge decay. The results of experiment approved that the PECVD SiO 2 /Si 3 N 4 double layers electrets on glass substrate has as good chargeability and charge stability in high temperature and high humidity environment as thermal oxidation or APCVD/LPCVD ones on silicon substrates. The experiment results indicated that a Si 3 N 4 layer no less than 50 nm is necessary for good charge stability in high temperature and a Si 3 N 4 layer thicker than 500 nm decreases the chargeability. Even a 2 nm Si 3 N 4 layer is enough to significantly improve the charge stability in high humidity environment. Thick SiO 2 layer can increase the surface potential of electrets under the same charging condition and its charge stability in high temperature. However, the electrets with high surface potential also exhibit poor uniformity of charge stability in high humidity environment.展开更多
In this work, we have studied a new lead-free ceramic of（1-y）Bi1-xNdxFeO3-yBiScO3（0.05≤x≤0.15 and 0.05≤y≤0.15） prepared by a conventional solid-state method, and the influences of Nd and Sc content on their ph...In this work, we have studied a new lead-free ceramic of（1-y）Bi1-xNdxFeO3-yBiScO3（0.05≤x≤0.15 and 0.05≤y≤0.15） prepared by a conventional solid-state method, and the influences of Nd and Sc content on their phase structure and electrical properties were investigated in detail. The ceramics with 0.05≤x≤0.10 and 0.05≤y≤0.15 belong to an R3 c phase, and the rhombohedral-like and orthorhombic multiphase coexistence is established in the composition range of 0.125≤x≤0.15 and y=0. The electrical properties of the ceramics can be enhanced by modifying x and y values. The highest piezoelectric coefficient（d33～51 p C/N） is obtained in the ceramics with x=0.075 and y=0.125, which is superior to that of a pure BiFeO3 ceramic. In addition, a lowest dielectric loss（tan δ～0.095%, f=100 k Hz） is shown in the ceramics with x=0.15 and y=0 due to the involvement of low defect concentrations, and the improved thermal stability of piezoelectricity at 20–600℃ is possessed in the ceramics. We believe that the ceramics can play a meaningful role in the high-temperature lead-free piezoelectric applications.展开更多
文摘A low-voltage, low-power, and high-gain rail-to-rail operational amplifier （OpAmp） is presented. The replica-amplifier gain enhancement technique is applied to improve the DC gain of the amplifier, which does not degrade the output swing and is very suitable for low-voltage applications. In a 0. 18/μm standard CMOS process,a 1V OpAmp with rail-to-rail output is designed. For a load capacitance of 5 pF,simulation by HSPICE shows that this OpAmp achieves an effective open-loop DC gain of 65. 9dB,gain bandwidth of 70.28 MHz,and phase margin of 50 with a quiescent power dissipation of 156.7μW.
文摘A novel topology low-voltage high precision current reference based on subthreshold Metal-Oxide-Semiconductor Field Effect Transistors （MOSFETs） is presented. The circuit achieves a temperature-independent reference current by a proper combination current of two first-order temperature-compensation current references, which exploit the temperature characteristics of integrated poly2 resistors and the 1- V transconductance characteristics of MOSFET operating in the subthreshold region. The circuit, designed with the 1 st silicon 0.35 μm standard CMOS logic process technology, exhibits a stable current of about 2.25 μA with much low temperature coefficient of 3 × 10^-4μA/℃ in the temperature range of-40-150 ℃ at 1 V supply voltage, and also achieves a better power supply rejection ratio （PSRR） over a broad frequency. The PSRR is about -78 dB at DC and remains -42 dB at the frequency higher than 10 MHz. The maximal process error is about 6,7% based on the Monte Carlo simulation. So it has good process compatibility.
基金supported by the National Key Technologies R&D Program(2016YFB0901500)National Natural Science Foundation of China(51725206,51421002,51232005,and 51372131)
文摘Sodium-ion batteries （NIBs） show great prospect on the energy storage applications benefiting from thei low cost and the abundant Na resources despite the expected lower energy density compared wit lithium-ion batteries （LIBs）. To further enhance the competitive advantage, especially in energy densit3 developing the high-capacity carbon anode materials can be one of the effective approaches to realiz this goal. Herein, we report a novel carbon anode made from charcoal with a high capacity of ~400 Ah g i, wherein about 85% （〉330 mAh g^-1） of its total capacity is derived from the long plateau regio below ~0.1 V. which differs fiom those of typical hard carbon materials （~300 mAh g^-l） in NIBs but i similar to the graphite anode in LIBs. When coupled with air-stable Nao.gCuo.22Feo.3oMno.4802 oxid cathode, a high-energy density of ~240 Wh kg^-1 is achieved with good rate capability and cyclin stability. The discovery of this promising carbon anode is expected to further improve the energy densit of NIBs towards large-scale electrical energy storage.
基金financially supported by the National Basic Research Program of China (973 Program) (Grant No. 2007CB936302)the National Natural Science Foundation of China (Grant No. 20833002)
文摘We herein report the effective performance enhancement of the pentacene-based organic thin film transistors with silicon di- oxide dielectric by inserting a thin metal phthalocyanines interlayer between Au source/drain electrodes and the pentacene active layer. The threshold voltage decreased remarkably from ca. -20 V to a few volts （below -7.6 V） while the mobility in- creased 1.5-3 times after the insertion of the interlayer of only ca. 2 nm, which could be attributed to the reduction of the car- tier injection barrier. The results suggest a simple and effective way to achieve low-threshold-voltage pentacene-based organic thin film transistors with high mobility on silicon dioxide dielectric.
基金supported by the National Basic Research Program of China ("973" Program) (Grant No. 2009CB320300)
文摘In this paper, performance of PECVD SiO 2 /Si 3 N 4 double layers electrets with different thicknesses were investigated detailedly in respect of chargeability, storage charge stability in high temperature and reliability in high humidity environment. Samples with different thicknesses of Si 3 N 4 and SiO 2 were prepared on Pyrex 7740 glass substrates and characterized by isothermal and high humidity charge decay. The results of experiment approved that the PECVD SiO 2 /Si 3 N 4 double layers electrets on glass substrate has as good chargeability and charge stability in high temperature and high humidity environment as thermal oxidation or APCVD/LPCVD ones on silicon substrates. The experiment results indicated that a Si 3 N 4 layer no less than 50 nm is necessary for good charge stability in high temperature and a Si 3 N 4 layer thicker than 500 nm decreases the chargeability. Even a 2 nm Si 3 N 4 layer is enough to significantly improve the charge stability in high humidity environment. Thick SiO 2 layer can increase the surface potential of electrets under the same charging condition and its charge stability in high temperature. However, the electrets with high surface potential also exhibit poor uniformity of charge stability in high humidity environment.
基金supported by the National Natural Science Foundation of China(Grant Nos.51102173&51472169)the College of Materials Science and Engineering of Sichuan University
文摘In this work, we have studied a new lead-free ceramic of（1-y）Bi1-xNdxFeO3-yBiScO3（0.05≤x≤0.15 and 0.05≤y≤0.15） prepared by a conventional solid-state method, and the influences of Nd and Sc content on their phase structure and electrical properties were investigated in detail. The ceramics with 0.05≤x≤0.10 and 0.05≤y≤0.15 belong to an R3 c phase, and the rhombohedral-like and orthorhombic multiphase coexistence is established in the composition range of 0.125≤x≤0.15 and y=0. The electrical properties of the ceramics can be enhanced by modifying x and y values. The highest piezoelectric coefficient（d33～51 p C/N） is obtained in the ceramics with x=0.075 and y=0.125, which is superior to that of a pure BiFeO3 ceramic. In addition, a lowest dielectric loss（tan δ～0.095%, f=100 k Hz） is shown in the ceramics with x=0.15 and y=0 due to the involvement of low defect concentrations, and the improved thermal stability of piezoelectricity at 20–600℃ is possessed in the ceramics. We believe that the ceramics can play a meaningful role in the high-temperature lead-free piezoelectric applications.
