In this paper, we propose an effective VLS1 architecture of sub-pixel interpolation for motion compensation in the AVS HDTV decoder. To utilize the similar arithmetical operations of 15 luma sub-pixel positions, three...In this paper, we propose an effective VLS1 architecture of sub-pixel interpolation for motion compensation in the AVS HDTV decoder. To utilize the similar arithmetical operations of 15 luma sub-pixel positions, three types of interpolation filters are proposed. A simplified multiplier is presented due to the limited range of input in the chroma interpolation process. To improve the processing throughput, a parallel and pipelined computing architecture is adopted. The simulation results show that the proposed hardware implementation can satisfy the real-time constraint for the AVS HDTV （1 920× 1 088） 30 fps decoder by operating at 108 MHz with 38.18k logic gates. Meanwhile, it costs only 216 cycles to accomplish one macroblock, which means the B frame sub-pixel interpolation can be realized by using only one set of the proposed architecture under real-time constraints.展开更多
The fundamental aspects of digital broadcasting are its service flexibility and power savings, which make all-digital satellite broadcasting a viable and economic propositon compared with analog broadcasting. Tendenci...The fundamental aspects of digital broadcasting are its service flexibility and power savings, which make all-digital satellite broadcasting a viable and economic propositon compared with analog broadcasting. Tendencies in the development of digital television broadcasting are: (1) Stereophonic or two-language sound transmission with television in existing analog TV system, (2) Digital direct satellite broadcasting (D-DBS); (3)Digital high definition television (HDTV) Broadcasting.展开更多
In H.264,computational complexity and memory access of deblocking filters are variable,dependent on video contents.This paper proposes a VLSI architecture of deblocking filters with adaptive dynamic power,which avoids...In H.264,computational complexity and memory access of deblocking filters are variable,dependent on video contents.This paper proposes a VLSI architecture of deblocking filters with adaptive dynamic power,which avoids redundant computations and memory accesses by precluding the blocks that can be skipped.The vertical and horizontal edges are simulta-neously processed in an advanced scan order to speed up the decoder.As a result,dynamic power of the proposed architecture can be reduced adaptively(up to about 89%) for different videos,and the off-chip memory access is improved when compared to previous designs.Moreover,the processing capability of the proposed architecture is in particular appropriate for real-time deblocking of high-definition television(HDTV,1920×1080 pixels/frame,60 frames/s video signals) video operation at 62 MHz.Using the proposed architecture,power can be reduced by up to about 89% and processing time by from 25% to 81% compared with previous designs.展开更多
基金Project (No. 20051321B01) supported by the Science and Technology Development Project of Hangzhou,China
文摘In this paper, we propose an effective VLS1 architecture of sub-pixel interpolation for motion compensation in the AVS HDTV decoder. To utilize the similar arithmetical operations of 15 luma sub-pixel positions, three types of interpolation filters are proposed. A simplified multiplier is presented due to the limited range of input in the chroma interpolation process. To improve the processing throughput, a parallel and pipelined computing architecture is adopted. The simulation results show that the proposed hardware implementation can satisfy the real-time constraint for the AVS HDTV （1 920× 1 088） 30 fps decoder by operating at 108 MHz with 38.18k logic gates. Meanwhile, it costs only 216 cycles to accomplish one macroblock, which means the B frame sub-pixel interpolation can be realized by using only one set of the proposed architecture under real-time constraints.
文摘The fundamental aspects of digital broadcasting are its service flexibility and power savings, which make all-digital satellite broadcasting a viable and economic propositon compared with analog broadcasting. Tendencies in the development of digital television broadcasting are: (1) Stereophonic or two-language sound transmission with television in existing analog TV system, (2) Digital direct satellite broadcasting (D-DBS); (3)Digital high definition television (HDTV) Broadcasting.
基金Project (No. NSS’USA5978) supported by the National Science Foundation of the United States under the East Asia Pacific Program
文摘In H.264,computational complexity and memory access of deblocking filters are variable,dependent on video contents.This paper proposes a VLSI architecture of deblocking filters with adaptive dynamic power,which avoids redundant computations and memory accesses by precluding the blocks that can be skipped.The vertical and horizontal edges are simulta-neously processed in an advanced scan order to speed up the decoder.As a result,dynamic power of the proposed architecture can be reduced adaptively(up to about 89%) for different videos,and the off-chip memory access is improved when compared to previous designs.Moreover,the processing capability of the proposed architecture is in particular appropriate for real-time deblocking of high-definition television(HDTV,1920×1080 pixels/frame,60 frames/s video signals) video operation at 62 MHz.Using the proposed architecture,power can be reduced by up to about 89% and processing time by from 25% to 81% compared with previous designs.
