An asynchronous pipeline architecture for the low-power AES S-box

To obtain a low-power and compact implementation of the advanced encryption standard(AES)S-box,an asynchronous pipeline architecture over composite field arithmetic was proposed in this paper.Inthe presented S-box,some improvements were made as follows.(1)Level-sensitive latches were insertedin data path to block the propagation Of the dynamic hazards,which lowered the power of data path cir-cuit.(2)Operations of latches were controlled by latch controllers based on presented asynchronous se-quence element:LC-element,which utilized static asymmetric C-element to construct a simple and pow-er-efficient circuit structure.(3)Implementation of the data path circuit was a semi-custom standard-cellcircuit on 0.25μm complementary mental oxide semiconductor(CMOS)process;and the full-custom de-sign methodology was adopted in the handshake circuit design.Experimental results show that the result-ing circuit achieves nearly 46% improvement with moderate area penalty(11.7%)compared with the re-lated composite field S-box in power performance.The presented S-box circuit can be a hardware intelli-gent property(IP)embedded in the targeted systems such as wireless sensor networks(WSN),smart-cams and radio frequency identification(RFID).