UHF RFID阅读器中恒定调谐增益LC-VCO设计

设计了一种应用于UHFRFID阅读器的恒定调谐增益LC-VCO。VCO采用互补交叉耦合结构实现较高电源利用效率，偏置电路采用电压调节结构有效抑制电源引入的噪声。提出创新的分布式偏置容抗管阵列，以实现恒定调谐增益。电路采用TSMCO．18μmCMOSRF工艺设计。仿真结果表明，VCO的频率调谐范围为1．61～2．03GHz，在1MHz频偏处，相位噪声为-127dBc／Hz，电源电压1．8V，电路消耗的总电流为3．4mA。电路在保证低相位噪声和低电源噪声灵敏度的同时，工作频带内调谐增益的变化控制在±7%以内。

2.82～4.04GHz CMOS差分调谐LC VCO的设计

通过对SMIC 0.13μm CMOS工艺的反型MOS电容的特性研究与测试验证,实现了一个2.82~4.04GHz的低调谐增益变化、低子带频率间隔变化、差分调谐宽带电感电容压控振荡器(LC VCO)。测试结果显示,频率覆盖范围为2.82~4.04 GHz,子带间距变化从12~6.9 MHz,中心差分调谐增益从23~17 MHz/V,相位噪声在频偏1 MHz处为-113^-118 dBc/Hz。

带有电压比例缩放模块的低调谐曲线增益压控振荡器

本文介绍了一种利用电压比例缩放模块的低调谐曲线增益的压控振荡器.电压比例缩放模块由电阻分压网络和电流垛电路组成.电阻分压网络比例缩小压控振荡器的控制电压,进而能得到较低的调谐曲线增益.电流垛模块电路向控制电压节点注入或抽取电流提供不同的直流电位,实现将调谐曲线变为多个子调谐曲线.由于电流垛模块和电阻分压网络具有很好的线性度,因此所实现的压控振荡器具有更线性的调谐范围.仿真结果显示调谐增益曲线小于20 MHz/V,并且具有好的线性度.

基于0.18μm CMOS工艺的宽带LCVCO设计

介绍了LCVCO原理及实现超宽频率覆盖的实现方法。在此基础上设计了一个频率覆盖范围达1.022 GHz的宽带LCVCO,实现了1.092 GHz^2.114 GHz频段的覆盖,为了减小VCO增益KVCO的波动,采用了自控变容管阵列模块。设计的振荡器采用0.18μm RF CMOS工艺,在Cadence软件Spectre仿真工具上的仿真结果显示电路的压控增益KVCO控制在±37.5%之内,在2.1 GHz、1.5 GHz和1.1 GHz频率点上电路电流分别为2.1 mA4、.4 mA7、.5 mA,相噪分别为-118 dBc/Hz@1 MHz-、114 dBc/Hz@1 MHz-、114 dBc/Hz@1 MHz。

应用于PLL的高性能VCO设计

本文采用HLMC 55LP工艺,设计了一个输出频率范围为500M-1.5GHz的VCO(电压控制振荡器)。本文首先介绍VCO的工作原理及设计背景,同时着重介绍本设计中所使用的VCO设计方法及其优势。本次设计经过前后仿验证,在较宽的频率范围内得到稳定且较小的KVCO值。

A 3.01–3.82 GHz CMOS LC voltage-controlled oscillator with 6.29% VCO-gain variation for WLAN applications

A wideband low-phase-noise LC voltage-controlled oscillator （VCO） with low VCO gain （Kvco） vari- ation for WLAN fractional-N frequency synthesizer application is proposed and designed on a 0.13-μm CMOS process. In order to achieve a low Kvco variation, an extra switched varactor array was added to the LC tank with the conventional switched capacitor array. Based on the proposed switched varactor array compensation technique, the measured Kvco is 43 MHz/V with only 6.29% variation across the entire tuning range. The proposed VCO provides a tuning range of 23.7% from 3.01 to 3.82 GHz, while consuming 9 mA of quiescent current from a 2.3 V supply. The VCO shows a low phase noise of-121.94 dBc/Hz at 1 MHz offset, from the 3.6 GHz carrier.

A fractional-N frequency synthesizer for wireless sensor network nodes

This paper presents a fractional-N frequency synthesizer for wireless sensor network（WSN） nodes. The proposed frequency synthesizer adopts a phase locked loop（PLL） based structure, which employs an LC voltagecontrolled oscillator（VCO） with small VCO gain（KVCO） and frequency step（fstep） variations, a charge pump（CP）with current changing in proportion with the division ratio and a 20-bit △∑ modulator, etc. To realize constant KVCO and fstep, a novel capacitor sub-bands grouping method is proposed. The VCO sub-groups＇ sizes are arranged according to the maximal allowed KVCOvariation of the system. Besides, a current mode logic divide-by-2 circuit with inside-loop buffers ensures the synthesizer generates I/Q quadrature signals robustly. This synthesizer is implemented in a 0.13μm CMOS process. Measurement results show that the frequency synthesizer has a frequency span from 2.07 to 3.11 GHz and the typical phase noise is 86：34 dBc/Hz at 100 k Hz offset and 114：17 dBc/Hz at 1 MHz offset with a loop bandwidth of about 200 k Hz, which meet the WSN nodes＇ requirements.

A wide-band low phase noise LC-tuned VCO with constant K_(VCO)/ω_(osc) for LTE PLL

A wideband LC-tuned voltage-controlled oscillator（LC-VCO） applied in LTE PLL frequency synthesizers with constant AVco/ωosc is described.In order to minimize the loop bandwidth variations of PLL,a varactor array is proposed,which consists of a series of differential variable capacitor pairs and a series of single-pole double-throw（SPDT） switches to connect Vtune or Vdd.The switches are controlled by switching bits.With this scheme,the ratio of KV =（？）Cvar/（？）Vtune and the capacitance value of the capacitor array maintains relatively constant; furthermore,the loop bandwidth of the PLL fluctuation is suppressed.The 3.2—4.6-GHz VCO for multi-band LTE PLL is fabricated in a 0.13-μm RF-CMOS process.The VCO exhibits a maximum variation of AVCO/ωosc of only±4%.The VCO also exhibits a low phase-noise of-124 dBc/Hz at a 1-MHz offset frequency and a low current consumption of 18.0 mA with a 1.2-V power supply.

A wideband frequency synthesizer with VCO and AFC co-design for fast calibration

A wideband fractional-N frequency synthesizer is implemented in a 65 nm CMOS process.It employs a wideband LC voltage-controlled oscillator（VCO） with optimized VCO gain（KVCO/and a sub-band step to improve automatic frequency calibration（AFC） efficiency at negligible expense of phase noise performance.An agile AFC is realized by direct mapping based on the division ratio,and optional redundant counting and comparing calibration is introduced accommodating PVT variations,which samples the reference clock using the prescaled VCO output as a discriminating clock.A charge pump with switched charging current is adopted to compensate for the loop bandwidth variation.Measurement results show this directly-mapped AFC locates the target sub-band in 100 ns and only needs 1.2 s for redundant calibration.The frequency synthesizer spans a frequency range from 0.62 to 1.52 GHz,with phase noise of-86 dBc/Hz at 10 kHz offset and-122 dBc/Hz at 1 MHz offset while consuming 9.76 mA from a 1.2 V supply.