Three-dimensional（3D） crossbar array architecture is one of the leading candidates for future ultra-high density nonvolatile memory applications. To realize the technological potential, understanding the reliability...Three-dimensional（3D） crossbar array architecture is one of the leading candidates for future ultra-high density nonvolatile memory applications. To realize the technological potential, understanding the reliability mechanisms of the3 D RRAM array has become a field of intense research. In this work, the endurance performance of the 3D 1D1 R crossbar array under the thermal effect is investigated in terms of numerical simulation. It is revealed that the endurance performance of the 3D 1D1 R array would be seriously deteriorated under thermal effects as the feature size scales down to a relatively small value. A possible method to alleviate the thermal effects is provided and verified by numerical simulation.展开更多
存内计算(Computing In Memory,CIM)在人工智能神经网络的卷积运算方面具有巨大的应用潜力。基于忆阻器阵列的多位存内计算由于具备写入速度快、与互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺兼容等特点,...存内计算(Computing In Memory,CIM)在人工智能神经网络的卷积运算方面具有巨大的应用潜力。基于忆阻器阵列的多位存内计算由于具备写入速度快、与互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺兼容等特点,有望成为解决“内存墙”的有效手段。然而,当前多位存内计算电路架构面临输出延时高和能耗大的问题,主要原因为传统感知放大器的性能制约,为此本文提出了一种低延时低能耗多位电流型感知放大器(Low-delay Low-power Multi-bit Current-mode Sense Amplifier,LLM-CSA),通过减少传统CSA电路工作状态数量、简化工作时序来优化功能;采用新型低位检测模块的电路设计思路,来多层次系统性地降低输出延时并优化能耗。使用中芯国际40 nm低漏电逻辑工艺(SMIC40 nm LL),利用Cadence电路设计平台,仿真验证所提LLM-CSA的功能和延时-能耗性能。通过对比分析发现:LLM-CSA比传统CSA输出延时降低1.42倍,能量消耗降低1.56倍。进一步地,以一种4 bit输入、4 bit权重、11 bit输出的忆阻器阵列多位存内计算架构为应用,对比验证所提LLM-CSA的性能:与基于传统CSA的存内计算系统相比,新架构延时降低1.18倍,能耗降低1.03倍。LLM-CSA的提出对促进感知放大器设计思路和忆阻器阵列存内计算架构的发展,具有一定的理论和现实意义。展开更多
In this paper, the bipolar resistive switching characteristic is reported in Ti/ZrO2/Pt resistive switching memory de- vices. The dominant mechanism of resistive switching is the formation and rupture of the conductiv...In this paper, the bipolar resistive switching characteristic is reported in Ti/ZrO2/Pt resistive switching memory de- vices. The dominant mechanism of resistive switching is the formation and rupture of the conductive filament composed of oxygen vacancies. The conduction mechanisms for low and high resistance states are dominated by the ohmic conduc- tion and the trap-controlled space charge limited current （SCLC） mechanism, respectively. The effect of a set compliance current on the switching parameters is also studied： the low resistance and reset current are linearly dependent on the set compliance current in the log-log scale coordinate; and the set and reset voltage increase slightly with the increase of the set compliance current. A series circuit model is proposed to explain the effect of the set compliance current on the resistive switching behaviors.展开更多
阻变存储器(resistive random access memory,RRAM)作为未来一种高性能的非挥发性存储器,具有面积小、操作电压低、兼容性好等特点.但是,在高集成存储器和频繁的写操作下,热串扰问题会严重影响RRAM的保持特性.严重情况下,热串扰问题甚...阻变存储器(resistive random access memory,RRAM)作为未来一种高性能的非挥发性存储器,具有面积小、操作电压低、兼容性好等特点.但是,在高集成存储器和频繁的写操作下,热串扰问题会严重影响RRAM的保持特性.严重情况下,热串扰问题甚至会造成一系列的错误翻转.因此,本文引入了一种高效的奇偶重排编码算法(parity rearrangement coding scheme,PRCoder)来有效缓解热串扰对RRAM的影响,并在算法层和电路层上分别进行设计与仿真.试验结果表明,PRCoder算法平均降低了32.7%的误翻转率,并同时只会在每一个存储行带来1bit的额外开销.此外,PRCoder仅仅带来0.3%的性能增加和0.008%的面积增加.展开更多
基金Project supported by the Opening Project of Key Laboratory of Microelectronics Devices&Integrated Technology,Institute of Microelectronics of Chinese Academy of Sciences,the National High Technology Research and Development Program of China(Grant No.2014AA032901)the National Natural Science Foundation of China(Grant Nos.61574166,61334007,61306117,61322408,61221004,and 61274091)+1 种基金Beijing Training Project for the Leading Talents in S&T,China(Grant No.Z151100000315008)the CAEP Microsystem and THz Science and Technology Foundation,China(Grant No.CAEPMT201504)
文摘Three-dimensional（3D） crossbar array architecture is one of the leading candidates for future ultra-high density nonvolatile memory applications. To realize the technological potential, understanding the reliability mechanisms of the3 D RRAM array has become a field of intense research. In this work, the endurance performance of the 3D 1D1 R crossbar array under the thermal effect is investigated in terms of numerical simulation. It is revealed that the endurance performance of the 3D 1D1 R array would be seriously deteriorated under thermal effects as the feature size scales down to a relatively small value. A possible method to alleviate the thermal effects is provided and verified by numerical simulation.
基金supported by the National Basic Research Program of China(Grant No.2011CBA00606)the National Natural Science Foundation of China(Grant Nos.61106106,11304237,61376099,and 11235008)the Specialized Research Fund for the Doctoral Program of Higher Education of China(Grant Nos.20130203130002 and 20110203110012)
文摘In this paper, the bipolar resistive switching characteristic is reported in Ti/ZrO2/Pt resistive switching memory de- vices. The dominant mechanism of resistive switching is the formation and rupture of the conductive filament composed of oxygen vacancies. The conduction mechanisms for low and high resistance states are dominated by the ohmic conduc- tion and the trap-controlled space charge limited current （SCLC） mechanism, respectively. The effect of a set compliance current on the switching parameters is also studied： the low resistance and reset current are linearly dependent on the set compliance current in the log-log scale coordinate; and the set and reset voltage increase slightly with the increase of the set compliance current. A series circuit model is proposed to explain the effect of the set compliance current on the resistive switching behaviors.
