Design of an OP-AMP Based on a LDO Regulator

An operational amplifier （OP-AMP） with a ground current of about 0.6μA is presented. Moreover, this amplifier reaps the benefits of incorporating a foldback current limiting circuit,which enables the low-dropout voltage regulator without the need of a special current limiting subblock. Therefore,the object of ultra-low power is realized because of a great reduction in transistors and current limbs.

A Novel Divider Based on Dual-Bit Algorithm

A novel divider based on dual-bit algorithm and its VLSI implementation are presented.Compared with the divider of MIPS microprocessor,it decreases the average executing cycles by 52.5% while its maximum delay is almost the same and its transistor count increases by 60%.Furthermore,the simulation result indicates that the power consumption decreases to 11.3% with the same processing ability.

An Accelerated Simulation Method for ELDRS of Bipolar Operational Amplifiers Using a Dose-Rate Switching Experiment

Through different dose-rate switching evaluation methods,the radiation-response rules of operational amplifiers are studied when the irradiation dose rate is switched from high to low under different radiation temperatures and total doses. The experimental results indicate that the response characteristics could be affected by the switching total doses, irradiation temperatures,and dose rates individually or together. Accelerated evaluation on the ELDRS can be realized by adopting a proper dose-rate switching method. Meanwhile, the irradiation time can also be reduced. Finally, the mechanisms of the difference between various radiation responses are analyzed.

FOUR-AXIS WIRE-EDM SIMULATION OF COMPLICATED MODELS

In the verification of wire electrical discharge machining （EDM）, the motion and the performance of the wire-EDM system are analyzed. The maximum inclining angle of the wire is calculated. The relevant judgment methods are used for the collision between the wire, the fixture, and the machining table. In the wire-EDM simulation, the generated solid model can he used to investigate programming results and to check the machining accuracy. The generation algorithm for the solid model in the simulation is solved based on Boolean operations. The wire swept volume for each cutting step is united to form the entire wire swept volume. Through Boolean subtraction between the stock model and the entire wire swept volume, the solid model in the wire-EDM simulation is generated. The method is also suitable for the wire path intersection occurred in cutting cone-shaped models. Finally, experiments are given to prove the method.

A Novel Charge-Transfer Matching Cell for High-Precision Correlation and Low-Power

A novel matching cell circuitry using charge transfer circuit technique for high precision correlation calculation is presented.The cell calculates the absolute value of the difference between two analog input voltages and amplifies the result.Amplification gain can be designed by the capacitance size in the cell and threshold voltage mismatch can be canceled automatically,thus high precision operation of the circuit is achieved.The circuit can be operated with low power dissipation of about 12μW at a frequency of 50MHz.Because of its simple structure and small silicon area,the matching cell is suitable to realize the correlation dealing with many template vectors that have many elements in a chip.

Development status and prospect of cold chain logistics of fruits,vegetables,and agricultural products based on intelligent technology

The cold chain in the production area of fruits and vegetables is the primary link to reduce product loss and improve product quality,but it is also a weak link.With the application of big data technology in cold chain logistics,intelligent devices,and technologies have become important carriers for improving the efficiency of cold chain logistics in fruit and vegetable production areas,extending the shelf life of fruits and vegetables,and reducing fruit and vegetable losses.They have many advantages in fruit and vegetable pre-cooling,sorting and packaging,testing,warehousing,transportation,and other aspects.This article summarizes the rapidly developing and widely used intelligent technologies at home and abroad in recent years,including automated guided vehicle intelligent handling based on electromagnetic or optical technology,intelligent sorting based on sensors,electronic optics,and other technologies,intelligent detection based on computer vision technology,intelligent transportation based on perspective imaging technology,etc.It analyses and studies the innovative research and achievements of various scholars in applying intelligent technology in fruit and vegetable cold chain storage,sorting,detection,transportation,and other links,and improves the efficiency of fruit and vegetable cold chain logistics.However,applying intelligent technology in fruit and vegetable cold chain logistics also faces many problems.The challenges of high cost,difficulty in technological integration,and talent shortages have limited the development of intelligent technology in the field of fruit and vegetable cold chains.To solve the current problems,it is proposed that costs be controlled through independent research and development,technological innovation,and other means to lower the entry threshold for small enterprises.Strengthen integrating intelligent technology and cold chain logistics systems to improve data security and system compatibility.At the same time,the government should introduce relevant policies,provide necessary financial support,and establish talent training mechanisms.Accelerate the development and improvement of intelligent technology standards in the field of cold chain logistics.Through technological innovation,cost control,talent cultivation,and policy guidance,we aim to promote the upgrading of the agricultural industry and provide ideas for improving the quality and efficiency of fruit and vegetable cold chain logistics.

An 80dB Dynamic Range ΣΔ Modulator for Low-IF GSM Receivers

A high-resolution,200kHz signal bandwidth,third-order single-loop single-bit ε△ modulator used in low-IF GSM receivers is presented. The modulator is implemented with fully differential switched capacitor circuits in standard 0. 6μm 2P2M CMOS technology. The modulator uses two balanced reference voltages of ±1V,and is driven by a single 26MHz clock signal. The measurement results show that,with an oversampling ratio of 64, the modulator achieves an 80.6dB dynamic range,a 71.8dB peak SNDR,and a 73.9dB peak SNR in the signal bandwidth of 200kHz. The modulator dissipates 15mW static power from a single 5V supply.

Using Symbolic Computation to Exactly Solve the Integrable Broer-Kaup Equations in （2＋1）-Dimensional Spaces

The extended tanh method is further improved by generalizing the Riccati equation and introducing its twenty seven new solutions. As its application, the (2+ 1)-dimensional Broer-Kaup equation is investigated and then its fifty four non-travelling wave solutions have been obtained. The results reported in this paper show that this method is more powerful than those, such as tanh method, extended tanh method, modified extended tanh method and Riccati equation expansion method introduced in previous literatures.

SVM with Quadratic Polynomial Kernel Function Based Nonlinear Model One-step-ahead Predictive Control

A support vector machine (SVM) with quadratic polynomial kernel function based nonlinear model one-step-ahead predictive controller is presented. The SVM based predictive model is established with black-box identification method. By solving a cubic equation in the feature space, an explicit predictive control law is obtained through the predictive control mechanism. The effect of controller is demonstrated on a recognized benchmark problem and on the control of continuous-stirred tank reactor (CSTR). Simulation results show that SVM with quadratic polynomial kernel function based predictive controller can be well applied to nonlinear systems, with good performance in following reference trajectory as well as in disturbance-rejection.

Similar Single-Difference Model and Its Algorithm for Solving GPS Monitoring Deformation Directly at Single Epoch

A new similar single-difference mathematical model (SS-DM) and its corresponding algorithmare advanced to solve the deformationof monitoring point directly in singleepoch. The method for building theSSDM is introduced in detail, and themain error sources affecting the accu-racy of deformation measurement areanalyzed briefly, and the basic algo-rithm and steps of solving the deform-ation are discussed.In order to validate the correctnessand the accuracy of the similar single-difference model, the test with fivedual frequency receivers is carried outon a slideway which moved in plane inFeb. 2001. In the test,five sessions areobserved. The numerical results oftest data show that the advanced mod-el is correct.

Remanufacturing closed-loop supply chain network design based on genetic particle swarm optimization algorithm

As the huge computation and easily trapped local optimum in remanufacturing closed-loop supply chain network (RCSCN) design considered, a genetic particle swarm optimization algorithm was proposed. The total cost of closed-loop supply chain was selected as fitness function, and a unique and tidy coding mode was adopted in the proposed algorithm. Then, some mutation and crossover operators were introduced to achieve discrete optimization of RCSCN structure. The simulation results show that the proposed algorithm can gain global optimal solution with good convergent performance and rapidity. The computing speed is only 22.16 s, which is shorter than those of the other optimization algorithms.

An 85mW 14-bit 150MS/s Pipelined ADC with a Merged First and Second MDAC

A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.

One-parameter quasi-filled function algorithm for nonlinear integer programming

A definition of the quasi-filled function for nonlinear integer programming problem is given in this paper. A quasi-filled function satisfying our definition is presented. This function contains only one parameter. The properties of the pro- posed quasi-filled function and the method using this quasi-filled function to solve nonlinear integer programming problem are also discussed in this paper. Numerical results indicated the efficiency and reliability of the proposed quasi-filled function algo- rithm.

The determination of the link with the smallest end-to-end network latency in ethernet architecture

Ethernet fundamental and its data transmission model are introduced in brief and end-to-end network latency was analyzed in this paper. On the premise of not considering transmission quality and transmission cost, latency was the function of the rest of network resource parameter (NRP). The relation between the number of nodes and that of end-to-end links was presented. In ethernet architecture, the algorithm to determine the link with the smallest latency is a polynomial issue when the number of network nodes is limited, so it can be solved by way of polynomial equations. Latency measuring is the key issue to determine the link with the smallest network latency. 3-node brigade (regiment) level network centric warfare (NCW) demonstration platform was studied and the latency between the detectors and weapon control stations was taken as an example. The algorithm of end-to-end network latency and link information in NCW was presented. The algorithm program based on Server/Client architecture was developed. The data transmission optimal link is one whose end-to-end latency is the smallest. This paper solves the key issue to determine the link whose end-to-end latency is the smallest in ethernet architecture. The study can be widely applied to determine the optimal link which is in the complex network environment of multiple service provision points.

Design of area and power efficient Radix-4 DIT FFT butterfly unit using floating point fused arithmetic

In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.

Model-based testing with UML applied to a roaming algorithm for Bluetooth devices

In late 2001, the Object Management Group issued a Request for Proposal to develop a testing profile for UML 2.0. In June 2003, the work on the UML 2.0 Testing Profile was finally adopted by the OMG. Since March 2004, it has become an official standard of the OMG. The UML 2.0 Testing Profile provides support for UML based model-driven testing. This paper introduces a methodology on how to use the testing profile in order to modify and extend an existing UML design model for test issues. The application of the methodology will be explained by applying it to an existing UML Model for a Bluetooth device.

Research on the fully fuzzy time-cost trade-off based on genetic algorithms

It is very difficult to estimate exact values of time and cost of an activity in project scheduling process because many uncertain factors, such as weather, productivity level, human factors etc. , dynamically affect them during project implementation process. A GAs-based fully fuzzy optimal time-cost trade-off model is presented based on fuzzy sets and genetic algorithms (GAs). In tihs model all parameters and variables are characteristics by fuzzy numbers. And then GAs is adopted to search for the optimal solution to this model. The method solves the time-cost trade-off problems under an uncertain environment and is proved practicable through a giving example in ship building scheduling.

On New Invariant Solutions of Generalized Fokker-Planck Equation

The generalized one-dimensional Fokker-Planck equation is analyzed via potential symmetry method and the invariant solutions under potential symmetries are obtained. Among those solutions, some are new and first reported.

Multi-line code: A low complexity revocable fingerprint template for cancelable biometrics

A low computational cost cancelable fingerprint template, namely the multi-line codes was proposed. The formulation of a single-line code involves the inspection of minutiae distribution along a straight line constructed based on the reference minutia. Multi-line code is introduced to elevate the performance by combining several single-line codes. Experiments were carried out on a few FVC databases. It has been proven that the proposed method yields relatively low computational complexity as compared to existing minutiae distribution-based methods, while preserving the performance. The equal error rate obtained for FVC2002 DB1 is 4.69% in stolen-key case, and the total arithmetic operations utilized are 14 520 additions and zero multiplication.

Optical readout uncooled infrared imaging detector using knife-edge filter operation

An optical readout uncooled infrared （IR） imaging detector of bimaterial cantilever array using knife-edge filter operation （KEFO） is demonstrated. The angle change of each cantilever in a focal plane array （FPA） can be simultaneously detected with a resolution of 10.5 degree. A deformation magnifying substrate-free micro-cantilever unit with multi-fold interval metaUized legs is specially designed and modeled. A FPA with 160×160 pixels is fabricated and thermal images with noise equivalent temperature difference （NETD） of 400 mK are obtained by this imaging detector.