A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage l...A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the driver-array method, With a capacity to work up to 500 MHz, the proposed circuit, which is simulated and fabricated using SMIC 0.18-pm 1.8-V digital CMOS technology, consumes less power than previously reported designs.展开更多
In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and...In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cas-code voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations.展开更多
片上缓存资源是片上路由器的重要组成部分,其结构好坏直接关系到片上互联网络的实现复杂度、整体性能及功耗开销。鉴于异步电路的握手工作方式,异步路由器一般采用基于移位寄存器的异步FIFO(First In First Out)实现片上缓冲,这种结构...片上缓存资源是片上路由器的重要组成部分,其结构好坏直接关系到片上互联网络的实现复杂度、整体性能及功耗开销。鉴于异步电路的握手工作方式,异步路由器一般采用基于移位寄存器的异步FIFO(First In First Out)实现片上缓冲,这种结构导致了报文传输延迟及数据翻转次数增加。提出一种基于层次位线缓冲的异步FIFO结构,设计实现了一种新的异步路由器结构。相对于传统异步路由器,新的异步路由器能够有效降低路由器设计的硬件复杂度,减少数据的冗余翻转,降低功耗。实验结果表明在相同配置的情况下,新异步路由器面积降低了39.3%;当异步FIFO深度为8的时候,新异步路由器能够获得41.1%的功耗降低。展开更多
基金the 973 Program of China (Grant No.G1999032903)the National Science Fund for Distinguished Young Scholars (Grant No.60025101)the Major Program of National Natural Science Foundation of China (Grant No.90707002)
文摘A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the driver-array method, With a capacity to work up to 500 MHz, the proposed circuit, which is simulated and fabricated using SMIC 0.18-pm 1.8-V digital CMOS technology, consumes less power than previously reported designs.
基金This work was supported in part by the National Natural Science Foundation of China ( Grant No.69973039) and National Science Foundation of USA (Grant No. 9988441) .
文摘In view of changing the type of energy conversion in CMOS circuits, this paper investigates low power CMOS circuit design, which adopts a gradually changing power clock. First, we discuss the algebraic expressions and the corresponding properties of clocked power signals. Then the design procedure is summed up for converting complementary CMOS logic gates employing DC power to the power-clocked CMOS gates employing AC power. On this basis, the design of differential cas-code voltage switch logic (DCVSL) circuits employing AC power clocks is proposed. The PSPICE simulations using a sinusoidal power-clock demonstrate that the designed power-clocked DCVSL circuit has a correct logic function and low power characteristics. Finally, an interface circuit to convert clocked signals into the standard logic levels of a CMOS circuit is proposed, and its validity is verified by computer simulations.
文摘片上缓存资源是片上路由器的重要组成部分,其结构好坏直接关系到片上互联网络的实现复杂度、整体性能及功耗开销。鉴于异步电路的握手工作方式,异步路由器一般采用基于移位寄存器的异步FIFO(First In First Out)实现片上缓冲,这种结构导致了报文传输延迟及数据翻转次数增加。提出一种基于层次位线缓冲的异步FIFO结构,设计实现了一种新的异步路由器结构。相对于传统异步路由器,新的异步路由器能够有效降低路由器设计的硬件复杂度,减少数据的冗余翻转,降低功耗。实验结果表明在相同配置的情况下,新异步路由器面积降低了39.3%;当异步FIFO深度为8的时候,新异步路由器能够获得41.1%的功耗降低。
