Currently, 1 bit or 2 bit signal quantization is widely used in satellite navigation software receivers. The bit-wise parallel algorithm has been proposed for 1 bit and 2 bit signal quantization, which performs correl...Currently, 1 bit or 2 bit signal quantization is widely used in satellite navigation software receivers. The bit-wise parallel algorithm has been proposed for 1 bit and 2 bit signal quantization, which performs correlation with high efficiency. In order to improve the performance of the correlator, this paper proposes a new 1.5 bit quantization method. Theoretical analyses are made from the aspects of complexity and quantization loss, and performance comparison between 1.5 bit quantization correlator and traditional correlators is discussed. The results show that the 1.5 bit quantization algorithm can save about 30 percent complexity under similar quantization loss, reduce more than 0.5 dB signal noise ratio（SNR） loss under similar complexity. It shows great performance improvement for correlators of satellite navigation software receivers.展开更多
At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed i...At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.展开更多
基金supported by the National Natural Science Foundation of China(61101076413741376147017)
文摘Currently, 1 bit or 2 bit signal quantization is widely used in satellite navigation software receivers. The bit-wise parallel algorithm has been proposed for 1 bit and 2 bit signal quantization, which performs correlation with high efficiency. In order to improve the performance of the correlator, this paper proposes a new 1.5 bit quantization method. Theoretical analyses are made from the aspects of complexity and quantization loss, and performance comparison between 1.5 bit quantization correlator and traditional correlators is discussed. The results show that the 1.5 bit quantization algorithm can save about 30 percent complexity under similar quantization loss, reduce more than 0.5 dB signal noise ratio（SNR） loss under similar complexity. It shows great performance improvement for correlators of satellite navigation software receivers.
文摘At high speeds and high resolution, the Pipeline ADCs are becoming popular. The options of different stage resolutions in Pipelined ADCs and their effect on speed, power dissipation, linearity and area are discussed in this paper. The basic building blocks viz. Op-Amp Sample and Hold circuit, sub converter, D/A Converter and residue amplifier used in every stage is assumed to be identical. The sub converters are implemented using flash architectures. The paper implements a 10-bit 50 Mega Samples/Sec Pipelined A/D Converter using 1, 1.5, 2, 3, 4 and 5 bits/stage conversion techniques and discusses about its impact on speed, power, area, and linearity. The design implementation uses 0.18 μm CMOS technology and a 3.3 V power supply. The paper concludes stating that a resolution of 2 bits/stage is optimum for a Pipelined ADC and to reduce the design complexity, we may go up to 3 bits/stage.
