本文回顾和梳理了当前片上雷达(Radar on Chip,RoC)的架构和射频前端、天线及信号处理等芯片化研究进展,以及基于异质异构集成、3D先进封装技术的雷达系统集成实现方案。在此基础上,从物理形态、实现工艺及技术发展等方面对片上雷达未...本文回顾和梳理了当前片上雷达(Radar on Chip,RoC)的架构和射频前端、天线及信号处理等芯片化研究进展,以及基于异质异构集成、3D先进封装技术的雷达系统集成实现方案。在此基础上,从物理形态、实现工艺及技术发展等方面对片上雷达未来发展趋势进行了分析,指出基于硅基半导体工艺,片上集成多路雷达收发前端、波形产生及信号处理等雷达功能单元,实现片上系统(System on Chip,SoC);或者通过异质异构及先进封装技术,将高度集成的雷达芯片集成在一个封装内,实现封装系统(System in Package,SiP),从而满足雷达系统微型化、轻重量、低成本和低功耗的发展需求。同时,基于芯片化可扩充多通道阵列模块也有望构建大型复杂阵列雷达系统。该方案为未来小型化武器装备提供有效的探测感知手段,也为蓬勃发展的民用雷达提供可行的技术路径。展开更多
Due to its low electrical loss and low process cost, a glass interposer has been developed to provide a compelling alternative to the silicon-based interposer for packaging of future 2-D and 3-D ICs. In this study,thr...Due to its low electrical loss and low process cost, a glass interposer has been developed to provide a compelling alternative to the silicon-based interposer for packaging of future 2-D and 3-D ICs. In this study,through glass vias(TGVs) are used to implement 3-D inductors for minimal footprint and large quality factor. Using the inductors and parallel plate capacitors, a compact 3-D Wilkinson power divider is designed and analyzed.Compared with some reported power dividers, the proposed TGV-based circuit has an ultra-compact size and excellent electrical performance.展开更多
Thanks to the emerging 3D integration technology, The multiprocessor system on chips （MPSoCs） can now integrate more IP cores on chip with improved energy efficiency. However, several severe challenges also rise up ...Thanks to the emerging 3D integration technology, The multiprocessor system on chips （MPSoCs） can now integrate more IP cores on chip with improved energy efficiency. However, several severe challenges also rise up for 3D ICs due to the die-stacking architecture. Among them, power supply noise becomes a big concern. In the paper, we investigate power supply noise （PSN） interactions among different cores and tiers and show that PSN variations largely depend on task assignments. On the other hand, high integration density incurs a severe thermal issue on 3D ICs. In the paper, we propose a novel task scheduling framework considering both the PSN and the thermal issue. It mainly consists of three parts. First, we extract current stimuli of running tasks by analyzing their power traces derived from architecture level simulations. Second, we develop an efficient power delivery network （PDN） solver to evaluate PSN magnitudes efficiently. Third, we propose a heuristic algorithm to solve the formulated task scheduling problem. Compared with the state-of-the-art task assignment algorithm, the proposed method can reduce PSN by 12% on a 2 × 2 × 2 3D MPSoCs and by 14% on a 3 × 3 × 3 3D MPSoCs. The end-to-end task execution time also improves as much as 5.5% and 7.8% respectively due to the suppressed PSN.展开更多
文摘本文回顾和梳理了当前片上雷达(Radar on Chip,RoC)的架构和射频前端、天线及信号处理等芯片化研究进展,以及基于异质异构集成、3D先进封装技术的雷达系统集成实现方案。在此基础上,从物理形态、实现工艺及技术发展等方面对片上雷达未来发展趋势进行了分析,指出基于硅基半导体工艺,片上集成多路雷达收发前端、波形产生及信号处理等雷达功能单元,实现片上系统(System on Chip,SoC);或者通过异质异构及先进封装技术,将高度集成的雷达芯片集成在一个封装内,实现封装系统(System in Package,SiP),从而满足雷达系统微型化、轻重量、低成本和低功耗的发展需求。同时,基于芯片化可扩充多通道阵列模块也有望构建大型复杂阵列雷达系统。该方案为未来小型化武器装备提供有效的探测感知手段,也为蓬勃发展的民用雷达提供可行的技术路径。
基金Projected supported by the National Natural Science Foundation of China(Nos.61771268,61571248,U1709218)the Science and Technology Fund of Zhejiang Province(No.2015C31090)+1 种基金the Natural Science Foundation of Zhejiang(No.LY17F040002)the K.C.Wong Magna Fund in Ningbo University
文摘Due to its low electrical loss and low process cost, a glass interposer has been developed to provide a compelling alternative to the silicon-based interposer for packaging of future 2-D and 3-D ICs. In this study,through glass vias(TGVs) are used to implement 3-D inductors for minimal footprint and large quality factor. Using the inductors and parallel plate capacitors, a compact 3-D Wilkinson power divider is designed and analyzed.Compared with some reported power dividers, the proposed TGV-based circuit has an ultra-compact size and excellent electrical performance.
基金This work was supported by the National Natural Science Foundation of China under Grant Nos. 61401008 and 61602022, and the State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences, under Grant No. CARCH201602.
文摘Thanks to the emerging 3D integration technology, The multiprocessor system on chips （MPSoCs） can now integrate more IP cores on chip with improved energy efficiency. However, several severe challenges also rise up for 3D ICs due to the die-stacking architecture. Among them, power supply noise becomes a big concern. In the paper, we investigate power supply noise （PSN） interactions among different cores and tiers and show that PSN variations largely depend on task assignments. On the other hand, high integration density incurs a severe thermal issue on 3D ICs. In the paper, we propose a novel task scheduling framework considering both the PSN and the thermal issue. It mainly consists of three parts. First, we extract current stimuli of running tasks by analyzing their power traces derived from architecture level simulations. Second, we develop an efficient power delivery network （PDN） solver to evaluate PSN magnitudes efficiently. Third, we propose a heuristic algorithm to solve the formulated task scheduling problem. Compared with the state-of-the-art task assignment algorithm, the proposed method can reduce PSN by 12% on a 2 × 2 × 2 3D MPSoCs and by 14% on a 3 × 3 × 3 3D MPSoCs. The end-to-end task execution time also improves as much as 5.5% and 7.8% respectively due to the suppressed PSN.
