Reconfigurable implementation ARP based on depth threshold in 3D-HEVC

Aiming at the high computational complexity and low efficiency of the advanced residual prediction(ARP)algorithm in 3 dimension high-efficiency video coding(3D-HEVC),the relationship between the depth value and ARP is analyzed.A fast ARP algorithm based on the depth value is proposed,which is implemented on the reconfigurable array processor developed by the project team.It uses a reconfigurable method to realize flexible switching between interview-ARP and tem-poral ARP.Experimental results show that while keeping the coding rate and the peak signal-to-noise ratio(PSNR)basically unchanged,the coding time of the six test sequences is reduced by 16.21%on average compared with HTM16.1.In contrast with non-reconfiguration,the average coding time is reduced by 52%,so the computational efficiency is improved.

A simplified hardware-friendly contour prediction algorithm in 3D-HEVC and parallelization design

After the extension of depth modeling mode 4(DMM-4)in 3D high efficiency video coding(3D-HEVC),the computational complexity increases sharply,which causes the real-time performance of video coding to be impacted.To reduce the computational complexity of DMM-4,a simplified hardware-friendly contour prediction algorithm is proposed in this paper.Based on the similarity between texture and depth map,the proposed algorithm directly codes depth blocks to calculate edge regions to reduce the number of reference blocks.Through the verification of the test sequence on HTM16.1,the proposed algorithm coding time is reduced by 9.42%compared with the original algorithm.To avoid the time consuming of serial coding on HTM,a parallelization design of the proposed algorithm based on reconfigurable array processor(DPR-CODEC)is proposed.The parallelization design reduces the storage access time,configuration time and saves the storage cost.Verified with the Xilinx Virtex 6 FPGA,experimental results show that parallelization design is capable of processing HD 1080p at a speed above 30 frames per second.Compared with the related work,the scheme reduces the LUTs by 42.3%,the REG by 85.5%and the hardware resources by 66.7%.The data loading speedup ratio of parallel scheme can reach 3.4539.On average,the different sized templates serial/parallel speedup ratio of encoding time can reach 2.446.

基于块编码特点的压缩视频质量增强算法

针对现有压缩视频质量增强算法未能充分利用压缩视频特点的问题,研究了视频编码与压缩视频质量增强任务之间的本质关系,并针对性地设计了一种基于三维卷积神经网络(3D convolutional neural network, 3D-CNN)的非对齐压缩视频质量增强算法。实验结果表明:相较于高效视频编码(high efficiency video coding, HEVC)标准H.265,所提算法在低延迟(low delay, LD)配置下且量化参数(quantization parameter, QP)为37时,峰值信噪比(peak signal-to-noise ratio, PSNR)提升了0.465 2 dB;相较于数据压缩会议(data compression conference, DCC)中提出的多帧引导的注意力网络(multi-frame guided attention network, MGANet)方法,该算法PSNR的增长量提升了15.1%。

基于HEVC的三维视频编码关键技术述评

综述了基于高效率视频编码HEVC(high efficiency video coding)标准的两种扩展,即MV-HEVC(high efficiency video coding based multiview)和3D-HEVC(high efficiency video coding based 3D video coding)的工作原理及其编码工具,分析了3D-HEVC模型的特点、编码模块与方法,并将3D-HEVC与MV-HEVC进行了性能对比.总结发现,由于3D-HEVC采用纹理视频加深度格式来合成虚拟视点,从而降低了大量的编码码率,可方便应用于3D电视、自由立体视点电视和3D数字电影等多种三维体验中.随着智能移动设备的发展,手持终端采用3D-HEVC支持多视点3D视频将会成为未来的研究趋势.

Wedge template optimization and parallelization of depth map in intra-frame prediction algorithms

To reduce the computational complexity and storage cost caused by wedge segmentation algorithm,a scheme of simplifying wedge matching is proposed.It takes advantage of the correlation of the wedge separation line of depth map and the direction of intra-prediction for 3D high-efficiency video coding(3D-HEVC).According to the difference of wedge segmentation between adjacent edge and opposite edge,a set only including 104×4 wedgelet templates is given.By expanding of the wedge wave of a certain minimum unit,a simple separation line acquisition method for different size of depth block is put forward.Furthermore,based on the array processor(DPR-CODEC)developed by project team,an efficient parallel scheme of the improved wedge segmentation mode prediction is introduced.By the scheme,prediction unit(PU)size can be changed randomly from 4×4 to 8×8,16×16,and 32×32,which is more in line with the needs of the HEVC standard.Veri-fied with test sequence in HTM16.1 and the Xilinx virtex-6 field programmable gate array(FPGA)respectively,the experiment results show that the proposed methods save 99.2%of the storage space and 63.94%of the encoding time,the serial/parallel acceleration ratio of each template reaches 1.84 in average.The coding performance,storage and resource consumption are considered for both.