Physical simulations and experimental results of 4H-SiC MESFETs on high purity semi-insulating substrates

In this paper we report on DC and RF simulations and experimental results of 4H-SiC metal semiconductor field effect transistors （MESFETs） on high purity semi-insulating substrates. DC and small-signal measurements are compared with simulations. We design our device process to fabricate n-channel 4H-SiC MESFETs with 100 #m gate periphery. At 30 V drain voltage, the maximum current density is 440 mA/mm and the maximum transconductance is 33 mS/mm. For the continuous wave （CW） at a frequency of 2 GHz, the maximum output power density is measured to be 6.6 W/mm, with a gain of 12 dB and power-added efficiency of 33.7%. The cut-off frequency （fT） and the maximum frequency （fmax） are 9 GHz and 24.9 GHz respectively. The simulation results of fT and fmax are 11.4 GHz and 38.6 GHz respectively.

Advanced SPICE-Modeling of 4H-SiC MESFETs

A modified drain source current suitable for simulation program with integrated circuit emphasis （SPICE） simulations of SiC MESFETS is presented in this paper. Accurate modeling of SiC MESFET is achieved by introducing three parameters in Triquint＇s own model （TOM）. The model, which is single piece and continuously differentiable, is verified by measured direct current （DC） I-V curves and scattering parameters （up to 20 GHz）.

Experimental and numerical analysis of the multi-recessed gate structure for microwave silicon carbide power MESFETs

This paper reports that multi-recessed gate 4H-SiC MESFETs （metal semiconductor filed effect transistors） with a gate periphery of 5-mm are fabricated and characterized.The multi-recessed region under the gate terminal is applied to improve the gate-drain breakdown voltage and to alleviate the trapping induced instabilities by moving the current path away from the surface of the device.The experimental results demonstrate that microwave output power density,power gain and power-added efficiency for multi-finger 5-mm gate periphery SiC MESFETs with multi-recessed gate structure are about 29%, 1.1dB and 7% higher than those of conventional devices fabricated in this work using the same process.

Characteristics and optimization of 4H-SiC MESFET with a novel p-type spacer layer incorporated with a field-plate structure based on improved trap models

A novel structure of 4H-SiC MESFETs is proposed that focuses on surface trap suppression.Characteristics of the device have been investigated based on physical models for material properties and improved trap models.By comparing with the performance of the well-utilized buried-gate incorporated with a field-plate （BG-FP） structure,it is shown that the proposed structure improves device properties in comprehensive aspects. A p-type spacer layer introduced in the channel layer suppresses the surface trap effect and reduces the gate-drain capacitance（C_（gd）） under a large drain voltage.A p-type spacer layer incorporated with a field-plate improves the electric field distribution on the gate edge while the spacer layer induces less C_（gd） than a conventional FP.For microwave applications,4H-SiC MESFET for the proposed structure has a larger gate-lag ratio in the saturation region due to better surface trap isolation from the conductive channel.For high power applications,the proposed structure is able to endure higher operating voltage as well.The maximum saturation current density of 460 mA/mm is yielded.Also,the gate-lag ratio under a drain voltage of 20 V is close to 90%.In addition,5%and 17.8%improvements in f_T and f_（max） are obtained compared with a BG-FP MESFET in AC simulation,respectively.Parameters and dimensions of the proposed structure are optimized to make the best of the device for microwave applications and to provide a reference for device design.