A novel low-cost sub-50nm poly-Si gate patterning technology is proposed and experimentally demonstrated.The technology is resolution-independent,ie.,it does not contain any critical photolithographic steps.The nano-s...A novel low-cost sub-50nm poly-Si gate patterning technology is proposed and experimentally demonstrated.The technology is resolution-independent,ie.,it does not contain any critical photolithographic steps.The nano-scale masking pattern for gate formation is formed according to the image transfer of an edge-defined spacer.Experimental results reveal that the resultant gate length,about 75 to 85 percent of the thickness,is determined by the thickness of the film to form the spacer.From SEM photograph,the cross-section of the poly-Si gate is seen to be an inverted-trapezoid,which is useful to reduce the gate resistance.展开更多
A comprehensive way to design a sub 50nm SADG MOSFET with the ability of being fabricated by improved CMOS technique is described.Under this way,the gate length and thickness of Si island of DG device show many diffe...A comprehensive way to design a sub 50nm SADG MOSFET with the ability of being fabricated by improved CMOS technique is described.Under this way,the gate length and thickness of Si island of DG device show many different scaling limits for various elements.Meanwhile,the spacer insulator shows a kind of width thickness on device drain current and circuit speed.A model about that effect is developed and offers design consideration for future.A new design of channel doping profile,called SCD,is also discussed here in detail.The DG device with SCD can achieve a good balance between the volume inversion operation mode and the control of V th .Finally,a guideline to make a SADG MOSFET is presented.展开更多
阐述如何使用NormalCu机型来沉积小线宽50nm产品的Barrier&Seed层,通过调制偏压电压及时间,改善了台阶覆盖性,避免了小线宽产品在开口处overhang的形成,提升了Normal机型工艺极限。使得制品缺陷、电性、良率和可靠性与RFx Cu机型在...阐述如何使用NormalCu机型来沉积小线宽50nm产品的Barrier&Seed层,通过调制偏压电压及时间,改善了台阶覆盖性,避免了小线宽产品在开口处overhang的形成,提升了Normal机型工艺极限。使得制品缺陷、电性、良率和可靠性与RFx Cu机型在最终的产品性能上表现一致,在50nm Nor Flash平台上顺利量产使用。展开更多
文摘A novel low-cost sub-50nm poly-Si gate patterning technology is proposed and experimentally demonstrated.The technology is resolution-independent,ie.,it does not contain any critical photolithographic steps.The nano-scale masking pattern for gate formation is formed according to the image transfer of an edge-defined spacer.Experimental results reveal that the resultant gate length,about 75 to 85 percent of the thickness,is determined by the thickness of the film to form the spacer.From SEM photograph,the cross-section of the poly-Si gate is seen to be an inverted-trapezoid,which is useful to reduce the gate resistance.
文摘A comprehensive way to design a sub 50nm SADG MOSFET with the ability of being fabricated by improved CMOS technique is described.Under this way,the gate length and thickness of Si island of DG device show many different scaling limits for various elements.Meanwhile,the spacer insulator shows a kind of width thickness on device drain current and circuit speed.A model about that effect is developed and offers design consideration for future.A new design of channel doping profile,called SCD,is also discussed here in detail.The DG device with SCD can achieve a good balance between the volume inversion operation mode and the control of V th .Finally,a guideline to make a SADG MOSFET is presented.
文摘阐述如何使用NormalCu机型来沉积小线宽50nm产品的Barrier&Seed层,通过调制偏压电压及时间,改善了台阶覆盖性,避免了小线宽产品在开口处overhang的形成,提升了Normal机型工艺极限。使得制品缺陷、电性、良率和可靠性与RFx Cu机型在最终的产品性能上表现一致,在50nm Nor Flash平台上顺利量产使用。
