A novel single event upset reversal in 40-nm bulk CMOS 6T SRAM cells

In advanced technologies, single event upset reversal(SEUR) due to charge sharing can make the upset state of SRAM cells recover to their initial state, which can reduce the soft error for SRAMs in radiation environments. By using the full 3D TCAD simulations, this paper presents a new kind of SEUR triggered by the charge collection of the Off-PMOS and the delayed charge collection of the On-NMOS in commercial 40-nm 6 T SRAM cells. The simulation results show that the proposed SEUR can not occur at normal incidence,but can present easily at angular incidence. It is also found that the width of SET induced by this SEUR remains the same after linear energy transfer(LET) increases to a certain value. In addition, through analyzing the effect of the spacing, the adjacent transistors, the drain area, and some other dependent parameters on this new kind of SEUR, some methods are proposed to strengthen the recovery ability of SRAM cells.

6-T CMOS SRAM单元稳定性分析及设计优化

介绍了一种由两个交叉耦合反向器构成的6-晶体管(6-T)存储单元的噪声容限分析方法。对6-T CMOS SRAM单元的稳定性作了分析及仿真。借助SPICE和MATLAB工具,对存储单元在数据保持和数据读取时的稳定性、数据写入过程中的可靠性及其之间的关系进行了深入研究。对可能影响噪声容限的因素,如单元比、上拉比、MOS管的阈值电压、位线预充电压、电源电压以及温度进行了仿真讨论,并从中得到合适的电路设计参数。流片结果表明,理论分析与实测数据相符。分析数据对基于CSMC 0.5μm CMOS工艺的SRAM电路设计优化具有指导作用。

一种使用浮动电源线嵌入式超低功耗SRAM的设计

为了解决存储单元的亚阈值泄漏电流问题,分析了在深亚微米下静态随机存储器(SRAM)6-T存储单元静态功耗产生的原因,提出了一种可以有效减小SRAM静态功耗浮动电源线的结构,并分析在此结构下最小与最优的单元数据保持电压;最后设计出SRAM的一款适用于此结构的高速低功耗灵敏放大器电路.仿真测试表明,使用浮动结构的SRAM的静态功耗较正常结构SRAM的静态功耗大大减小.