建立了单粒子多位翻转的测试方法和数据处理方法,在此基础上开展了体硅90nm SRAM重离子单粒子多位翻转的实验研究。通过分析单粒子多位翻转百分比、均值、尺寸等参数随线性能量转移(linear energy transfer,LET)的变化关系,表明了纳米...建立了单粒子多位翻转的测试方法和数据处理方法,在此基础上开展了体硅90nm SRAM重离子单粒子多位翻转的实验研究。通过分析单粒子多位翻转百分比、均值、尺寸等参数随线性能量转移(linear energy transfer,LET)的变化关系,表明了纳米尺度下器件单粒子多位翻转的严重性,指出了单粒子多位翻转对现有重离子单粒子效应实验方法和预估方法带来的影响。构建了包含多个存储单元的全三维器件模型,数值模拟研究了不同阱接触布放位置对单粒子多位翻转电荷收集的影响机制,表明阱电势扰动触发多单元双极放大机制是导致单粒子多位翻转的主要因素,减小阱接触与存储单元之间的距离是降低单粒子多位翻转的有效方法。展开更多
In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present...In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are given. The results are obtained through Monte-Carlo simulations.展开更多
In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness a...In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.展开更多
文摘建立了单粒子多位翻转的测试方法和数据处理方法,在此基础上开展了体硅90nm SRAM重离子单粒子多位翻转的实验研究。通过分析单粒子多位翻转百分比、均值、尺寸等参数随线性能量转移(linear energy transfer,LET)的变化关系,表明了纳米尺度下器件单粒子多位翻转的严重性,指出了单粒子多位翻转对现有重离子单粒子效应实验方法和预估方法带来的影响。构建了包含多个存储单元的全三维器件模型,数值模拟研究了不同阱接触布放位置对单粒子多位翻转电荷收集的影响机制,表明阱电势扰动触发多单元双极放大机制是导致单粒子多位翻转的主要因素,减小阱接触与存储单元之间的距离是降低单粒子多位翻转的有效方法。
文摘In this paper, we present a solution to the ultra low voltage inverter by adding a keeper transistor in order to make the semi-floating-gate more stable and to reduce the current dissipation. Moreover, we also present a differential ULV inverter and elaborate on the reliability and fault tolerance of the gate. The differential ULV gate compared to both a former ULV gate and standard CMOS are given. The results are obtained through Monte-Carlo simulations.
文摘In this paper, novel ultra low voltage (ULV) dual-rail NOR gates are presented which use the semi-floating-gate (SFG) structure to speed up the logic circuit. Higher speed in the lower supply voltages and robustness against the input signal delay variations are the main advantages of the proposed gates in comparison to the previously reported domino dual-rail NOR gates. The simulation results in a typical TSMC 90 nm CMOS technology show that the proposed NOR gate is more than 20 times faster than conventional dual-rail NOR gate.
