建立了单粒子多位翻转的测试方法和数据处理方法,在此基础上开展了体硅90nm SRAM重离子单粒子多位翻转的实验研究。通过分析单粒子多位翻转百分比、均值、尺寸等参数随线性能量转移(linear energy transfer,LET)的变化关系,表明了纳米...建立了单粒子多位翻转的测试方法和数据处理方法,在此基础上开展了体硅90nm SRAM重离子单粒子多位翻转的实验研究。通过分析单粒子多位翻转百分比、均值、尺寸等参数随线性能量转移(linear energy transfer,LET)的变化关系,表明了纳米尺度下器件单粒子多位翻转的严重性,指出了单粒子多位翻转对现有重离子单粒子效应实验方法和预估方法带来的影响。构建了包含多个存储单元的全三维器件模型,数值模拟研究了不同阱接触布放位置对单粒子多位翻转电荷收集的影响机制,表明阱电势扰动触发多单元双极放大机制是导致单粒子多位翻转的主要因素,减小阱接触与存储单元之间的距离是降低单粒子多位翻转的有效方法。展开更多
A specially designed experiment is performed for investigating gate-induced drain leakage （GIDL） current in 90nm CMOS technology using lightly-doped drain （LDD） NMOSFET. This paper shows that the drain bias VD has...A specially designed experiment is performed for investigating gate-induced drain leakage （GIDL） current in 90nm CMOS technology using lightly-doped drain （LDD） NMOSFET. This paper shows that the drain bias VD has a strong effect on GIDL current as compared with the gate bias VG at the same drain-gate voltage VDG. It is found that the difference between ID in the off-state ID - VG characteristics and the corresponding one in the off-state ID - VD characteristics, which is defined as IDIFF, versus VDG shows a peak. The difference between the influences of VD and VG on GIDL current is shown quantitatively by IDIFF, especially in 90nm scale. The difference is due to different hole tunnellings, Furthermore, the maximum IDIFF（IDIFF,MAX） varies linearly with VDG in logarithmic coordiuates and also VDG at IDIFF,MAX with VF which is the characteristic voltage of IDIFF, The relations are studied and some related expressions are given.展开更多
文摘建立了单粒子多位翻转的测试方法和数据处理方法,在此基础上开展了体硅90nm SRAM重离子单粒子多位翻转的实验研究。通过分析单粒子多位翻转百分比、均值、尺寸等参数随线性能量转移(linear energy transfer,LET)的变化关系,表明了纳米尺度下器件单粒子多位翻转的严重性,指出了单粒子多位翻转对现有重离子单粒子效应实验方法和预估方法带来的影响。构建了包含多个存储单元的全三维器件模型,数值模拟研究了不同阱接触布放位置对单粒子多位翻转电荷收集的影响机制,表明阱电势扰动触发多单元双极放大机制是导致单粒子多位翻转的主要因素,减小阱接触与存储单元之间的距离是降低单粒子多位翻转的有效方法。
基金Project supported by the National High Technology Research and Development Program of China （Grant No 2003AA1Z1630） and the National Natural Science Foundation of China （Grant No 60376024）.
文摘A specially designed experiment is performed for investigating gate-induced drain leakage （GIDL） current in 90nm CMOS technology using lightly-doped drain （LDD） NMOSFET. This paper shows that the drain bias VD has a strong effect on GIDL current as compared with the gate bias VG at the same drain-gate voltage VDG. It is found that the difference between ID in the off-state ID - VG characteristics and the corresponding one in the off-state ID - VD characteristics, which is defined as IDIFF, versus VDG shows a peak. The difference between the influences of VD and VG on GIDL current is shown quantitatively by IDIFF, especially in 90nm scale. The difference is due to different hole tunnellings, Furthermore, the maximum IDIFF（IDIFF,MAX） varies linearly with VDG in logarithmic coordiuates and also VDG at IDIFF,MAX with VF which is the characteristic voltage of IDIFF, The relations are studied and some related expressions are given.
